This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

hyperlink 6657 Waiting for other side to come up

Hi,

I am running the hyperlink example. 

I have set to Asynchronous mode :

/* Synchronized token passing between two endpoints using CPU IO */
// #define hyplnk_EXAMPLE_TEST_CPU_TOKEN_EXCHANGE

/* Synchronized token passing between two endpoints using EDMA IO */
//#define hyplnk_EXAMPLE_TEST_DMA_TOKEN_EXCHANGE

/* Asynchronous block transfers using CPU (memset/memcmp) */
#define hyplnk_EXAMPLE_TEST_CPU_BLOCK_XFER

/* Asynchronous block transfers using EDMA */
//#define hyplnk_EXAMPLE_TEST_DMA_BLOCK_XFER

I am running the hyperlink example on one 6657 EVM which connected to DC power in NO BOOT state and to JTAG  and the second 6657 EVM connected to PCIe in PCIe boot mode.  When running the example on the First EVM I get the following LOG :

[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Aug 24 2014:21:06:26
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c495; TX=0x000cc315
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00006201
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x03060c19; lock = 1
Waiting for other side to come up ( 1)
Waiting for other side to come up ( 2)
Waiting for other side to come up ( 3)
Waiting for other side to come up ( 4)
Waiting for other side to come up ( 5)
Waiting for other side to come up ( 6)
Waiting for other side to come up ( 7)
Waiting for other side to come up ( 8)

...

.

.

.

Please advise,

Ivgeni.

  • Hi,

    I think other side device is not connected properly. This is a exepted log for this case.

    Please provide more detail about your setup connection detail. Have you running the Hyperlink example project on both EVM?

    Thanks,

  • Hi,

    I am running EVM example only on single EVM. the second is connected to the PC via PCIe in PCIe boot mode.

    This is the reason I am working in asynchronous mode.

    Ivgeni

  • Hi,

    The basic configuration is required for other side device, such as enabling the power domain and performing the SerDes configuration of the HyperLink.

    Refer below thread for more information

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/193332.aspx

    Thanks,

  • Hi.

    Is The basic configuration is :

    //////////////////

    enable_module(mcm_pdctl, mcm_mdctl);//Enable Hyperlink module power

    CSL_tscEnable(); /* Enable the TSC */

    memset(dstBuf1, 0xFF, sizeof(dstBuf1));
    memset(dstBuf2, 0xFF, sizeof(dstBuf2));


    Hyperlink_config();//hyperlink configuration for Cppi mode

    ///////////////////////

    Thanks,

    Ivgeni.

  • Hi,

    Refer "hyplnkExampleSysSetup()" on Hyperlink example project for enabling the HyperLink power domain, and the SERDES configuration.

    Thanks,

  • Hi,

    I get this output, test is failed/ please advise :

    [C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Sep 3 2014:19:55:43
    About to do system setup (PLL, PSC, and DDR)
    Power domain is already enabled. You probably re-ran without device reset (which is OK)
    Constructed SERDES configs: PLL=0x00000064; RX=0x0046c495; TX=0x000cc315
    system setup worked
    About to set up HyperLink Peripheral
    ============== begin registers before initialization ===========
    Revision register contents:
    Raw = 0x4e901900
    Status register contents:
    Raw = 0x00002004
    Link status register contents:
    Raw = 0x00000000
    Control register contents:
    Raw = 0x00006201
    Control register contents:
    Raw = 0x00000000
    ============== end registers before initialization ===========
    SERDES_STS (32 bits) contents: 0x0c183061; lock = 1
    ============== begin registers after initialization ===========
    Status register contents:
    Raw = 0x04400005
    Link status register contents:
    Raw = 0xccf00cff
    Control register contents:
    Raw = 0x00006200
    ============== end registers after initialization ===========
    Waiting 5 seconds to check link stability
    Precursors 0 Analysis: 0,1,0,1,0,1,0,1
    Postcursors: 19 Analysis: 1,0,0,1,1,0,0,1
    Link seems stable
    About to try to read remote registers
    ============== begin REMOTE registers after initialization ===========
    Status register contents:
    Raw = 0x0440000b
    Link status register contents:
    Raw = 0xfdf0bdfa
    Control register contents:
    Raw = 0x00006200
    ============== end REMOTE registers after initialization ===========
    Peripheral setup worked
    About to read/write once
    fail 0 0
    hyplnkExampleCPUTokenExchange failed: 1
    Single write failed
    Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Sep 3 2014:19:55:43
    About to do system setup (PLL, PSC, and DDR)
    Power domain is already enabled. You probably re-ran without device reset (which is OK)
    Constructed SERDES configs: PLL=0x00000064; RX=0x0046c495; TX=0x000cc315
    system setup worked
    About to set up HyperLink Peripheral
    ============== begin registers before initialization ===========
    Revision register contents:
    Raw = 0x4e901900
    Status register contents:
    Raw = 0x00002004
    Link status register contents:
    Raw = 0x00000000
    Control register contents:
    Raw = 0x00006201
    Control register contents:
    Raw = 0x00000000
    ============== end registers before initialization ===========
    SERDES_STS (32 bits) contents: 0x0c183061; lock = 1
    ============== begin registers after initialization ===========
    Status register contents:
    Raw = 0x04400005
    Link status register contents:
    Raw = 0xccf00cff
    Control register contents:
    Raw = 0x00006200
    ============== end registers after initialization ===========
    Waiting 5 seconds to check link stability
    Precursors 0 Analysis: 0,1,0,1,0,1,0,1
    Postcursors: 19 Analysis: 1,0,1,0,0,1,1,0
    Link seems stable
    About to try to read remote registers
    ============== begin REMOTE registers after initialization ===========
    Status register contents:
    Raw = 0x0440000b
    Link status register contents:
    Raw = 0xfdf0bdfa
    Control register contents:
    Raw = 0x00006200
    ============== end REMOTE registers after initialization ===========
    Peripheral setup worked
    About to read/write once
    fail 0 0
    hyplnkExampleCPUTokenExchange failed: 1
    Single write failed

  • Hi,

    Have you command hyplnk_EXAMPLE_TEST_CPU_TOKEN_EXCHANGE test case in your code?

    /* Synchronized token passing between two endpoints using CPU IO */
    // #define hyplnk_EXAMPLE_TEST_CPU_TOKEN_EXCHANGE

    hyplnkExampleCPUTokenExchange failed printf come under the TOKEN_EXCHANGE test case. Please uncommand the test case on your code. For more information refer "hyplnkExampleIOCycle()" in hyplnkExample.c file.

    Thanks,

  • Hi,

    I changed to :


    /* Synchronized token passing between two endpoints using CPU IO */
    //#define hyplnk_EXAMPLE_TEST_CPU_TOKEN_EXCHANGE

    /* Synchronized token passing between two endpoints using EDMA IO */
    //#define hyplnk_EXAMPLE_TEST_DMA_TOKEN_EXCHANGE

    /* Asynchronous block transfers using CPU (memset/memcmp) */
    #define hyplnk_EXAMPLE_TEST_CPU_BLOCK_XFER

    /* Asynchronous block transfers using EDMA */
    //#define hyplnk_EXAMPLE_TEST_DMA_BLOCK_XFER
    //

    Now I get this error :

    ============== begin REMOTE registers after initialization ===========
    Status register contents:
    Raw = 0x0440000b
    Link status register contents:
    Raw = 0xfdf0bdfa
    Control register contents:
    Raw = 0x00006200
    ============== end REMOTE registers after initialization ===========
    Peripheral setup worked
    About to read/write once
    hyplnkExampleCPUBlockXfer failed: 3449
    Single write failed