Hi,
I am running the hyperlink example.
I have set to Asynchronous mode :
/* Synchronized token passing between two endpoints using CPU IO */
// #define hyplnk_EXAMPLE_TEST_CPU_TOKEN_EXCHANGE
/* Synchronized token passing between two endpoints using EDMA IO */
//#define hyplnk_EXAMPLE_TEST_DMA_TOKEN_EXCHANGE
/* Asynchronous block transfers using CPU (memset/memcmp) */
#define hyplnk_EXAMPLE_TEST_CPU_BLOCK_XFER
/* Asynchronous block transfers using EDMA */
//#define hyplnk_EXAMPLE_TEST_DMA_BLOCK_XFER
I am running the hyperlink example on one 6657 EVM which connected to DC power in NO BOOT state and to JTAG and the second 6657 EVM connected to PCIe in PCIe boot mode. When running the example on the First EVM I get the following LOG :
[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Aug 24 2014:21:06:26
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c495; TX=0x000cc315
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00006201
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x03060c19; lock = 1
Waiting for other side to come up ( 1)
Waiting for other side to come up ( 2)
Waiting for other side to come up ( 3)
Waiting for other side to come up ( 4)
Waiting for other side to come up ( 5)
Waiting for other side to come up ( 6)
Waiting for other side to come up ( 7)
Waiting for other side to come up ( 8)
...
.
.
.
Please advise,
Ivgeni.