SPI booting for C6657

Hi Ram,

The SPI boot mode is designed to address an SPI memory device. You can use the FPGA in place of the SPI memory but it would need to respond with the same timing as the memory. Some FPGAs include  memory capability. You would need to program the memory from your host processor before releasing the SOC from reset and include logic to emulate the SPI memory interface. I don't see any way that you could bridge the SPI interface from the SOC to the host without creating some local storage in the FPGA.

Regards, Bill

Hi,

as i planned like this, please correct me and clarify.

(1)As i am using the SPI boot mode, first i want to extract my application program (eg test.out file) to boot table format (eg:with hex conversion)which understands by RBL in the SPI boot mode. Then write this complete boot table from Host to FPGA using a FIFO in a memory place in FPGA for eg with address 0x testfile.Then how the DSP knows that it has to take this start address in SPI boot mode?i configure in this test.out file the core PLL and DDR3 PLL. so i hope once the RBL writes section by section from 0xtestfile in DSP memory then the right PLL for DSP and DDR3 PLL are configured.

(2)At the moment i dont' have the SPI interface working between the FPGA and the DSP. what i have to tell the FPGA from DSP, that it can configure SPI, how to do it?

(3) i am using the JTAG now to load my .out file, to configure and test my core PLL, DDR3, PCIE. Even we want in the future to boot up the DSP first through SPI interface with .outfile1 and re load every time with new .outfiles i.e .outfile2 with PCIE interface as these files are of bigger size compared to first outfile. do you think is it good idea?

Thanks,

Ram.

Hi,

please ignore my last post.

i got to know our FPGA does not include the memory capability. so i want to do the SPI booting as follows.

Take the bootapplication.outfile in the host and convert to the format understand by DSP-RBL in the host.It is defined in the spec as .outfile->Hex6x->Romparse->bootconvert6x->B2i2c then the output boottable goes from host to FPGA using FIFO and also from FPGA FIFO to DSP via SPI. so after starting writing my boottable in the FPGA-FIFO, i release dsp from reset, so the ROM bootloader waits for my data from FPGA FIFO. Then it boots in this way.

Do you think this is fine?

does TI has any .exe or any easy alternative that converts my .out file automatically in the B2i2c format to understand by RBL?

Do you have any information if some one done the SPI booting in this way?

Thanks,

Ram.

Hi Ram,

Fine. It is possible. Please refer DSP Boot loader user guide(SPRUGY5) for more information.

Thank you.

Hi,

i am using now a batch file from George written in other posts. This batch file converts the .outfile to .bin file.But if my .out file is big one it has some problems,may be i have to modify it to fit for big input files.

i am giving the SPI boot batch file as an attachment which i am using, Please see it and please tell me i can use this .bin file. And also also how can i extract this .bin file in my host and write into the FPGA FIFO.After that it will be written into the DSP via SPI interface where the RBL is waiting for the right boot format.

REM - Add utilities to PATH
REM set PATH=D:\CAX\TI\CCS_55\ccsv5\tools\compiler\c6000_7.4.1\bin;%PATH%
REM set PATH=D:\CAX\TI\CCS_55\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util\bconvert;%PATH%
REM set PATH=D:\CAX\TI\CCS_55\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util\btoccs;%PATH%
REM set PATH=D:\CAX\TI\CCS_55\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util\romparse;%PATH%
REM set PATH=C:\ti\_Projects\byteswapccs\Debug;%PATH%
REM set PATH=C:\ti\_Projects\bootbuild;%PATH%

REM - Create environment var to utilities
set IBL_PATH=D:\CAX\TI\CCS_55\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util
set PROJ_BYTESWAPCCS=D:\TestDsp_C6657\SPI_Boot\George_Boot_5040
set PROJ_BOOTBUILD=D:\BBC-SW\BBCoder\DspSw\StromboliDsp\TestDsp_C6657\SPI_Boot\George_Boot_5040

REM - Build the "simple" SPI bootable application and convert into a "binary" image to place in SPI NOR Flash
hex6x mySpiBoot.rmd
%IBL_PATH%\bconvert\bconvert64x -le mySpiBoot.btbl mySpiBoot.btbl.bcv64x

REM - Eliminated the following utility pair as the results were *NOT* producing desired results for use with SPI
%IBL_PATH%\btoccs\b2i2c mySpiBoot.btbl.bcv64x mySpiBoot.btbl.bcv64x.i2c
%IBL_PATH%\btoccs\b2ccs mySpiBoot.btbl.bcv64x.i2c mySpiBoot.btbl.bcv64x.i2c.ccs

REM - Alternative to above
REM %IBL_PATH%\btoccs\b2ccs mySpiBoot.btbl.bcv64x mySpiBoot.btbl.bcv64x.i2c.ccs

REM - Elimated the following utility as the results were *NOT* producing desired results for use with SPI (probably re-compile of romparse is needed for SPI)
REM %IBL_PATH%\romparse\romparse mySpiBoot.map

REM - Using "home-brewed" version of "romparse" to achieve desired results for use with SPI
%PROJ_BOOTBUILD%\bootbuild mySpiBoot.map

REM - Replaced TI's E2E recommended "byteswapccs" in lieu of the "ccs2bin" which appears to be working properly
REM %PROJ_BYTESWAPCCS%\byteswapccs mySpiBoot.btbl.bcv64x.i2c.ccs spirom_le.bin
%IBL_PATH%\btoccs\ccs2bin       i2crom.ccs spirom_le.bin
%IBL_PATH%\btoccs\ccs2bin -swap i2crom.ccs spirom_le.swap.bin

copy spirom_le.swap.bin D:\TestDsp_C6657\norwriter_evmc6657l\bin\app.bin 

Thanks,

Ram.

Hi Ram,

Please take a look at below link for converting .out file to .bin format

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/354771/1253899.aspx#1253899

Thanks,

Hi,

thanks for the link. i successfully converted my custom.out file to .bin file. 

As you  know, i don't have any NOR flash on custom board, i have to use this file in the following way to load into the DSP.

i have to extract this .bin file in my host into bytes(as i have to extract bytes sequentially?)and i write these bytes into the FPGA FIFO.After that it will be written into the DSP via SPI interface where the RBL is waiting for the right boot format. As i have to write this file into bytes of certain  bolcks of bytes with certain block size or can i write sequentially byte by byte into the FPGA FIFO?

thanks,

Ram.

Hi Bill,

thats perfectly fine.

but the .bin file i generated have to be extracted  in bytes sequentially and write these bytes sequentially into the FPAG fifo ?is it fine? or is there any special procedure to extract this .bin file to understand by RBL?

thanks,

Ram.