Team,
It seems that for KII the ECC feature of the DDR3 is not mandatory to use.
I found some info about it in:
- DDR3 Design Requirements for KI and KII - SPRABI1B section 2.6. There is a note about the DDR topologies supported with and without ECC.
- DDR3 Memory Controller User Guide - SPRUHN7A section 2.16 gives some details about disabling the ECC.
However some additional info would be helpful.
- The below post was listing the pins that can be left unused when ECC is not used in KI devices:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/226645.aspx
But seems to be removed in a later version.
Are the DDRCB pins the only one to leave unused/unconnected when ECC is not used?
The DDRCBx pins are not listed in any of the DDR3 related doc mentioned above. It is just listed in the device data manuals.
- In term of connectivity can you confirm that Figure 7 in DDR3 Design Requirements - SPRABI1B
Section 4.1.1 is an example to used discrete DDR3 without ECC? (as the DDRCBx are not shown).
Thanks and best regards,
Anthony
