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Read-Modify-Write module of DDR3 controller

Kzk
Genius 5785 points

Hello,

A read and write command by RMW will be issued as a pair? If the command which is 64bit aligned and multiple of 64bit from other master is issued to same address of DDR3 simultaneously, this command does not break into between a pair of commands which are issued by RWM, does it?

Regards,
Kazu

  • 0
    Genius 5785 points

    Please give me information. I saw the following description.

    The controller maintains coherence across all outstanding commands in the command FIFO whether or not they are affected by the RMW module and also follows the normal command arbitration outlined in section 2.6.1. The above RMW process for sub-quanta writes means the execution of the write command will be delayed compared to if the command was not sub-quanta and was 64-bit aligned.

    KeyStone II DDR3 Memory Controller User Guide (SPRUHN7A)
    2.16.1.1 Read-modify-write

    Does it occur coherence problem If each two master writes data into same address on DDR3 concurrently?

    The master A: Writes 8bit data into DDR3. This means that write and read command will be occured by RMW.
    The master B: Writes data into same address which is not sub-quanta and is 64-bit aligned.

    If the following scenario is occur, I think that the data will be corrupted by 3).
    1) Issue read command by A. 2) Issue write command by B. 3) Issue write command by A.

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru* 81335 points

    Hi Kazu,

    We are working on this post. Thank you for your patience.

    Thank you.

  • 0 in reply to Kzk
    TI__Mastermind 42545 points

    Hi Kazu,

    Does it occur coherence problem If each two master writes data into same address on DDR3 concurrently?


    The controller will maintain coherency across all commands irrespective of the master and irrespective whether any of those commands are RMW.


    The master A: Writes 8bit data into DDR3. This means that write and read command will be occured by RMW.
    The master B: Writes data into same address which is not sub-quanta and is 64-bit aligned.
    If the following scenario is occur, I think that the data will be corrupted by 3).
    1) Issue read command by A. 2) Issue write command by B. 3) Issue write command by A.


    In this case the controller will not execute the write from master B until the read and modified-write for master A is complete. Therefore, the sequence will be:

    1) issue read command by A. 2) Issue write command by A. 3) Issue write command by B.

     Regards, Bill