Unable to keep monolithic descriptors in MSMC(shared memory) for AIF2 TX(LTE DL) input

Hello,

Please assist me how to proceed further in this blocking issue.Since,I am unable to put monolithic descriptors in MSMC region for Aif2  TX side.

Regards,

Jeanne

Hi Jeanne,

basically, L2 memory access has less amount of delay than accessing MSMC and DDR3. DDR3 may cause page threshing if multiple cores try to access DDR at the same time especially through the same bridge (EDMA TC2, AIF2, BCP shares the bridge 7 to access the DDR) you may have to check your application not only from Core3 but also other cores if there are any other high priority tasks that try to access the MSMC and DDR3 at the same time.

There is no restriction like Tx and Rx descriptors are should be in the same kind of memory but you'd better try to move the TX descriptors to the same memory area and see, if the same problem occurs or not. if you use AxC channel and packet channel together on Tx side, those two memory regions should be in the same memory but I think this is not your case. (it looks you are using AxC channels only)

Checking Cache coherency is also one of the way. you can check the delay when you turn on and off the L1D cache and check what is the difference.

I'm not modem protocol level expert, so I could just give you check points based on HW point of view.

Regards,

Albert  

Hello Albert,

In the scenario that I mentioned above,my software runs only on core 3.

Moreover,Data is copied to Aif2 TX monolithic descriptors through DMA(that is,there exists a direct connection between FFTC and Aif2 ,So,FFTC Rx Queue is Aif2 input Transmit Queue ,). 

This implies that there shouldn't be cache coherency issue.

However,the strange part is that I am able to keep these descriptors in DDR3(with a little more sw cycles,for which you suggested the possible reason that- << EDMA TC2, AIF2, BCP shares the bridge 7 to access the DDR>>.It's ok.). 

But the issue is that I am unable to keep the descriptors in MSMC(,because of a large delay introduced).

That is,Point 5 of my previous post

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5.Second,with above monolithic descriptors moved to MSMC and executing AIF2 Loopback,the LTE downlink software doesn't work at all. While debugging,I observed that packets in MSMC are now not reaching AIF2 input queue at correct lte symbol time resulting in a large packet delay gradually ,followed by failure in lte dl software code execution on Core3.

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And yes,I am using AxC channels only

So,the major query is that-

Despite of the fact that MSMC is faster than DDR3, I am unable to keep them in MSMC.

Is there any specific hardware constraint from Aif2 or FFTc point of view?

Please advise.

Regards

Hi,

Normally, we expect better or similar performance from MSMC when compared to DDR.

DDR data goes through DDR controller in MSMC module and that means it makes more delay than MSMC memory direct access. there is no well known HW restriction about that access and I have never heard that kind of issue before from any customers. I'm still thinking there must be additional MSMC memory access or VBUS usage that may cause this delay. BTW, where is your linking RAM is it in the MSMC or L2? How about moving your linking RAM to the same place where your descriptors regions are located.

Regards,

Albert

Hi Albert,

I am using the internal linking RAM only.

Moreover, there are already existing buffers placed in all 3 levels of memory region - L2, MSMC and DDR3. But no issue is found till yet.

Now, as I move these AIF2 TX side descriptors(filled by DMA) to MSMC, the delay is introduced significantly.(while ,as provided in previous posts, no real-time delay is introduced while placing them in DDR3 )

So, I think that there should be some other reason for this delay.

Please advise

Regards,

Jeanne 

that's really weird. I've never seen the MSMC makes trouble even though it doesn't make any trouble on DDR3. I've seen the opposite case a lot (works on MSMC but trouble on DDR3) 

You already said you don't use L1D cache from MSMC.

this problem cannot be explained if you are not doing heavy MSMC access at the same time from multiple high priority DMAs or CPU access.

Regards,

Albert

Hello,

After the detailed analysis, I found that-

Besides FFTC-AIF2 direct connection, at FFTC Rx side, a monolithic descriptor in MSMC gets popped from FFTC RX FDQ but not reaches FFTC Rx queue (which is AIf2 TX queue) at correct time.

That is, internal DMA done by FFTC to fill packet in MSMC is taking large amount of time.

Is there any limitation of FFTC while feeding it's data output to MSMC?

Note: MSMC is not much accessed by CorePac/peripherals in our software(So, page thrashing might not get applied here).

Please guide me how to proceed further in this blocked scenario.

Regards,

Jeanne