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What should PC do when DSP read/write data from/to it through Outbound?

Hello, everyone:

    I'm debugging PCIe communication between C6678EVM and PC( Windows7 ). The Inbound transaction works fine.

    Now the DSP's outbound address is set to BAR3(0xF0000000). DSP writes some data to PCIe data space addr(0x60000000). How can PC receive these data? I found the data that PC read from 0xF0000000 is not the data that the DSP wrote to 0x60000000, but the data at 0xF0000000 in DSP.

    So what should the PC do when DSP read/write data from/to it through Outbound?


    Thank you in advance!

   

  • Could anybody help me, please?

  • Hi Fan,

    Refer MCSDK PCIe example project for PCIe inbound and outbound address translation.

    In MCSDK PCIe example DSP1 C6678 configured as RC and DSP2 C6678 configured as EP. Both DSPs BAR1 and BAR2 bar mask BAR-MASK = 0x03FFFFFF as i have to map with 256MByte.

    DSP1 Inbound address is 0x90000000 and Outbound address is 0x60000000

    DSP2 Inbound address is 0x60000000 and Outbound address is 0x90000000

    After configuring PCIE registers.it shows PCIE link is up. I able to write in the memory of 0x60000000.

    Please take a look at MCSDK PCIe example project (Path: \ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\PCIE_exampleProject)

    Please take a look at below e2e threads:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/305143/1063249.aspx#1063249

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/349074/1223005.aspx#1223005

    Thanks,

  • Hello, Ganapathi:

        Thank you very much for the reply.

        Yes, I do use the PCIe_examPleproject running in the C6678EVM with some necessary modifications.

        DSP Inbound address configs BAR1(0xF1400000) to DSP's dstBuf.buf(0x10820E00). The PC can read/write DSP's dstBuf.buf(0x10820E00) by reading/writing from/to BAR1(0xF1400000). It seems that the Inbound transaction works fine.

        Now I'm going on debugging the Outbound. DSP Outbound address is configed to BAR3(0xF0000000).

        In PC, a dataBuf is allocated to accept the data sent from DSP. 

        Should PC do some Inbound translation to config the address of dataBuf to BAR3(0xF0000000)? What settings should be done in PC in order to accept the data sent from DSP?

     

  • Hi Fan,

    Please share your test project. I will try to understand your test code and give possible solution.

    Thanks,

  • Hi, Ganapathi:

        Thank you very much for the reply.

        The attached project is the pcie_exampleProject which I modified the Inbound and Outbound settings. I'm trying to use this project to communicate with PC( with Os Win7 64).

        In the Inbound settings, the DSP's dstBuf.buf(0x10822200) is set to BAR1(0xF1400000).

        The Outbound address is set to BAR3(0xF0000000).

        I have already successfully used the software WinDriver on PC(with Os Win7 64) to read/write the DSP's dstBuf.buf. In WinDriver I wrote 0x12345678 to BAR1(0xF1400000) with offset 0, then I can get the data 0x12345678 at the address of DSP's dstBuf.buf(0x10822200). The attached "C6678 BAR0-5.docx" shows the results, which proves that the Inbound works fine as I talked before. So the PC(with Os Win7 64) can read/write from/to the DSP.

        Now what I want to do is to realized the process that the DSP read/write from/to the PC(with Os Win7 64). The Outbound settings is done in DSP, which is set to BAR3(0xF0000000). I want to know what settings should be done in PC(with Os Win7) in order to receive data from DSP.

        I also attached the WinDriver software(which could be used freely for 30 days without registration). Hope you could understand my questions and help me. Thank you!

    2337.PCIE_exampleProject - modified.zip

  • HI Ganapathi

    I am working on EVM6657 and window 7 PC. i want to transfer sampled data from the host PC(Root complex) to the DSP(endpoint) through PCIe communication. i downloaded 6657 FPGA v2 and Programing "IBL" on the EEPROM at bus address 0x51.then the PC is enumerated the C6657 and detected as Media controller in device manager.then i develop the PCIE driver using windriver using default value without changing any value of the BARs or Interrupts.

    my questions are:
    1. How to start to make the PC as Root complex and the DSP as endpoint.

    I found example in C:\ti\pdk_C6657_1_1_1_4\packages\ti\drv\pcie\example\sample , but both RC and EP are implemented on DSP device..if it is possible i want to develop RC code inside the Driver generated code.

    2.  i read PCIe use cases for keystone Device (SPRUGS6) pdf. but because i am new to this PCIe thing its difficult to me to understand most of the concept about BARs  and other configurable stuffs. is there any simple example that may clarify the over all concept of PCIe ?.

    thanks in advance.

    Regard Rediet.