Hello,
I'm entertaining the possibility of using a Keystone Multicore DSP in a high speed (>1GSPS) data acquisition application. We normally use FPGAs for this sort of thing. So, I'm investigating how to interface the high speed ADCs to the DSP. I learned that maybe the best way is to use an FPGA as an intermediary where the FPGA acquires the data from the ADC via LVDS ports and then uses the RapidIO to send the data to the DSP via the DSP SRapidIO ports. OK. So, I look at what it takes to use the RapidIO on an FPGA and discover that a RapidIO core costs anywhere from $15K to $27K depending upon the FPGA vendor. Well, this is no longer accurately described as "glue" logic as the cost dwarfs any other single cost in the whole prototype system! This of course is a DSP IC show stopper unless maybe I write the RapidIO myself from scratch. I'm not sure right now how involved that might be. I probably don't have to support the entire standard but only enough of the standard to get the ADC data to the DSP.
Does anyone have or know of any cost effective solutions of interfacing high speed ADCs to Keystone Multicore DSP devices?
Thank you.
