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how processor 32 address lines are connected to emif16 24 address lines

Hi,

I am working on EMIF16 to read data from FPGA. With 24-bit address lines of emif16, i am able to access only 16M address lines(i.e, 16M words = 32MB).But in data sheet of 6678, it is given that per chip you can address 64MB.

How to access 64MB of FPGA by emif16 with single chip select ?

I am using evaluation board for 6678.

Regards,

Vamshi

  • Hello Vamshi,

    I believe that your assessment is correct, that only 32 MB is supported per chip select.

    The footnote of table 2-2 of the C6678 datasheet mentions that 32 MB per chip select is supported for 16-bit NOR and SRAM. 

    http://www.ti.com/lit/ds/symlink/tms320c6678.pdf

    The above information is not available in EMIF16 user guide and it will be fixed into the next release of the EMIF16 user guide.

     

    Regards,

    Senthil

  • Thank you senthil,

    one more question to be answered is how these 24 address lines are connected to 32 address lines of processor.

    While testing emif, i have observed that one LSB bit is discarded and next 24 lines of processor is connected to emif16 24 address lines. Is this correct?

    Regards,

    Vamshi

  • Hello Vamshi,

    one more question to be answered is how these 24 address lines are connected to 32 address lines of processor.

    The 24 address lines are internally mapped to 24 least significant lines of 32 address lines. So when you change the address using 24 address lines, it will reflect on 24 least significant bits of the base address of EMIF CS space.

    While testing emif, i have observed that one LSB bit is discarded and next 24 lines of processor is connected to emif16 24 address lines. Is this correct?

    Do you mean that the FPGA A0 address pin is not connected to any signal ?

    Regards,

    Senthil