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C66x CorePac prefetch buffer size

Other Parts Discussed in Thread: 66AK2H12

Hello,

I am working on an Keystone II - 66AK2H12 on an EVMK2HX, ev.3 board and I need to analyze the accesses towards the MSMC memory sub-system.

So, my question is, how do the prefetch buffer inside XMC works? I mean:

HOW MANY data does the XMC prefetches as it receives a (L1D or L2) cache miss to an address whose corresponding MAR PFX bit is set to 1? Does it fill the full 8x128byte prefetch buffer?

I already read the section 7.5 on SPRUGW0C, and several presentations and PDF downloaded by your KB, but I found no answer

Best

Paolo Burgio

  • Paolo,

    Just to be clear it's not a 8x128B prefetch buffer, it's 8 128B prefetch buffers.  They should be viewed independently.  

    No, it will not simply fill up all the prefetch buffers simultaneously, but will work towards filling them up over time based on Slot that's allocated.   Note you could have different slots looking from data in two separate places back and forth, you would not want them to simply cancel each other out constantly.  Each slot would get one, and it would fill it's 128B buffer with that data (and the next associated slot has a prediction based on address changes - i.e. going up/down addresses) and then the other data array gets grabbed into another buffer based on it's slot, and the next associated slot would have a prediction based on which way it was going and it's address.  

    Of course, an access to a new location that wasn't in the prediction would have the next slot go off and grab data into the next available buffer for it's data.

    It really depends on the activity, and how quickly it's data is consumed as to if all the buffers are filled up w/ just one locations prefetching, but it won't happen if you're accessing more than one prefetchable location.

    Best Regards,

    Chad

  • Thank you very much Chad! Now I have some doubts on how the prediction actually works. Does it simply fetch "next" or "previous" data, depending maybe on the access pattern? Or is there some more complicated logic "under the hood"?

    Paolo

  • It's based on recent data pattern accesses only (the length be determined by prefetch buffers.)   But it's not going to 'remember' patterns over time period if that's what you're asking.  

    Best Regards,

    Chad

  • Hello Chad, and thanks again,

    So, what do you mean by "recent data patterns"? Does it understand "strided" patterns, that is, if I access, say, addresses 0x0, then 0x100, then 0x200, will it prefetch 0x300, 0x400 and so on?

    and most of all, since buffers are decoupled, does this mechanism work for 8 "access patterns" at the same time? (I guess no, but..)

    is there a whitesheet that describes the prefetch buffer behaviour in details? I didn't found any...

    the point is, I am doing research on Real-Time system, exploring the applicability of Keystone as a target platform, and I need to know as much as possible how the prefetch buf actually works to go on with my research. 

    BTW do you also know of anyone working on keystone as a possible RT platform?

    Best

    Paolo

  • Sorry..and In addition, do you know if there is a way to completely disable the prefetch buffer (i.e., without writing on the MAR registers for a specific chunk of memory?)

    Best

    Paolo

  • Paolo,

    I'll have to verify this, but I believe if it's doing base address offsets then it will predict strides.

    The recent access patterns are from reading data in incremental or decremental orders primarily.

    It can work for up to 8 access patterns, but that's probably going to be extremely rare situation coming from a single core at the same time.  

    There is no white paper on the prefetcher.

    By RT I'm assuming you mean real time.  If so, yes, most customers are using this as a RT platform using our RTOS, there's a forum dedicated to it.

    There's no way to globally disable Prefetcher.  You'd need to disable it individually via the MARs.

    Best Regards,

    Chad