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Rise time and fall time of C6654

Jeff Kuo
Prodigy 220 points
Hi
 
Would you help me check C6654 Coreclk rise and fall time spec?
Is mean -100mV to 100mV rise time or fall time between 50~350ps?
Jeff
  • 0
    TI__Mastermind 43660 points

    Hello Jeff,

    As documented in device datasheet, the PLL clock rise/fall time is in between 50ps to 350ps (10% to 90%) for 250mV peak to peak signal.

    The 10% to 90% range for 250mV peak to peak is -100mV to +100mV and 50ps to 350ps rise/fall time applies for -100mV to +100mV.

    Regards,

    Senthil

  • 0
    TI__Mastermind 42545 points

    Hi Jeff,

    Remember that this graph represents peak-to-peak differential voltage, similar to a scope capture from a differential probe. That's why the waveform is centered around 0V. The LJCB clock input can operate with input signals that have a differential peak-to-peak of greater than 250mV. The rise time specified is associated 10% to 90% within that minimum voltage window, even if the differential peak-to-peak voltage is greater. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 220 points

    Hi

    Do you mean measure peak-to-peak differential voltage 10% to 90%? or 250mV 10% to 90%?

  • 0 in reply to Jeff Kuo
    TI__Mastermind 42545 points

    Hi Jeff,

    When you measure the clock input differentially it will be centered around 0V. A valid clock input must be at least 250mV peak-to-peak which would appear as a waveform from -125mV to +125mV. The levels can be higher than 250mV but portion of the waveform of interest for rise time is that -125mV to +125mV section. We specify the rising and falling edge for 10% to 90% of that portion. 

    Regards, Bill