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66AK2H06: SPI Flash Size - SPI Boot flash and SPI data flash

Rams
Expert 1800 points
Other Parts Discussed in Thread: 66AK2H06

Hi,

For one of our custom board based on 66AK2H06, we are exploring the options for mounting 1Gig flash.  

But as per the SPI device configuration field description, the width bit has either 16 bit or 24 bit configuration which seems to limit the addressing to 128Mbit.  Does this mean that we cannot mount SPI flash bigger than 128Mbit?

Is that limitation only for SPI boot flash?  Is that possible to have another flash, bigger than 128Mbit on SPI bus 2 for some data storage?

Please clarify.

Regards

Rams

  • 0
    TI__Mastermind 43660 points

    Hello Rams,

    Yes, the SPI width bit has either 16 bit or 24 bit that limits the address spacing up to (224 =  16Mb). With this address spacing you can get the maximum memory space of 128Mb (16Mb x8).

    I think the SPI flash addressing limit is applicable even if you use it for data storage.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Expert 1800 points

    Hi Senthil,

    As the addressing limits are available in SPI boot mode configuration, we are wondering if the limit is applicable for non-boot SPI flashes on SPI bus?  Can you please confirm the fact that the addressing limit is applicable for non-boot SPI flash as well?

    Thanks

    Rams

  • 0 in reply to Rams
    Expert 1800 points

    Hi,

    I am seeking confirmation on the restriction for data storage flash because the response from TI did not strongly confirm this.  

    "I think the SPI flash addressing limit is applicable even if you use it for data storage"

    Your confirmation on this will helpful.

    If so, can this addressing limitation for data storage flash be relaxed in anyway?

    Regards

    Rams

    Note:

    We tried testing a 32MB Giga SPI flash device.  We added the driver and the device is detected.  But we could not write to the device successfully.  We are not sure whether this error is because of addressing restriction.

    / # flashcp -v /dev/shm/a /dev/mtd9

    Erasing block: 2560/2560 (100%)

    Writing kb: 10240/10240 (100%)

    Verifying kb: 0/10240 (0%) flashcp: verification mismatch at 0x0

    / # flashcp -v /dev/shm/a /dev/mtd10

    Erasing block: 2560/2560 (100%)

    Writing kb: 10240/10240 (100%)

    Verifying kb: 0/10240 (0%) flashcp: verification mismatch at 0x0

     

     

  • 0 in reply to Rams
    TI__Mastermind 43660 points

    Hello Rams,

    We are working on this post, will get back soon.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    TI__Guru** 114410 points

    16 bit and 24 bit addressing is only a restriction at boot times. For K2H at boot times, SPI boot supports only 16bit and 24 bit addressing so we can support only up to 24 bit addressing or 128Mbits. However, by modifying the SPI driver you should be able to support higher address space in non boot scenario because addressing essentially is taken care of in the SPI  protocol defined in datasheet from the flash device. For non –boot situations on EVM, I checked the PDK drivers and they are also setup to support only 24 bit addressing.

     In other keystone devices like K2E devices, we have extended support for 32 bit addressing during boot.

    I have shown the SPI protocol for 16 bit, 24 bit and 32 bit addressing in the K2E ROM code.

    For 16 bit addressing:

    SPI_READ_COMMAND >   ADDR [15:8] > ADDR[7:0]

     For 24 bit addressing

    SPI_READ COMMAND > ADDR [23:16] > ADDR [15:8] > ADDR[7:0]

     For 32 bit addressing:

    SPI_READ COMMAND > ADDR[31:24] >ADDR [23:16] > ADDR [15:8] > ADDR[7:0]

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Expert 1800 points

    Hi Rahul,

    Thanks a lot for the response.  Can you please attach the sample driver of K2E SPI driver code for reference?

    Thanks

    Rams

  • 0 in reply to Rams
    Expert 1800 points

    Hi,

    We are able to get 4 byte mode working for the flash.  Is mixed mode allowed in K2H SPI boot?  If we have a 32MB SPI flash,  is that possible to boot in default 24 bit addressing and switch to 32 bit addressing while starting kernel?

    It will allow us to have a bigger boot flash operating in mixed mode rather than having two SPI flashes for boot and data.

    Thanks

    Rams

  • 0 in reply to Rams
    TI__Guru** 114410 points

    Hi Rams,

    You will need to check with your SPI flash vendor or the datasheet for the flash device to check if this mode can be supported by the SPI READ command. The Boot ROM cannot determine the addressing of the SPI flash so we use boot switch settings to guide the Boot ROM to read the SPI flash. Once configured in 16 bit or 24 bit addressing, it will transmit SPI read signals using the appropriate addressing protocol.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Expert 1800 points

    Hi Rahul,

    Thanks.  We are able to use 32MB SPI flash and do SPI boot and switch to 32 bit addressing post boot.

    Regards

    Rams