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C6678 I2C Master Boot, DevStat not latching boot mode

M Imran Tahir
Prodigy 50 points

Hello,

I have come across an issue when trying to boot a c6678 custom board (based on the evm). It boots fine in no boot mode or I2C slave mode for POST, however in I2C master mode for NAND, it does not. The DEVSTAT register shows 00010021 instead of 0001082B expected from boot-mode GPIO pins status. Using a modified ibl.bin (for reduced DDR speed) for eeprom , which works well on the evm. Linux kernel from linux-c6x.org (nand.bin) is flashed into the nand device (NAND512R3A2SZA6E same as evm but later version) also works fine on evm. Mcsdk version: mcsdk_2_01_02_06.

My question is what can cause the device not to latch the boot mode pins status into the DevStat register in I2C master boot mode?

Many thanks,

Tahir

  • 0
    TI__Guru* 81335 points

    Hi Tahir,

    From my understanding POST also I2C master boot only. If the I2C slave address in 0x50 it loads POST. If the slave address in 0x51 it loads IBL. Please ensure to load the IBL in slave address 0x51.

    How the boot GPIO pins are interfaced with C6678 in custom board? In EVM, boot pins to DSP are driven by FPGA. Please refer EVMs schematic for more information.

    Thank you.

  • 0 in reply to Raja
    Prodigy 50 points

    Hi Rajasekaran,

    Thanks for your reply.

    Yes you are right, sorry I should have said I2C master boot works for 0x50 address (POST) but not for 0x51 (Nand). ibl.bin is written at 0x51 in the eeprom. So in summary:

    Boot Mode Pins (GPIO0-12)          DEVSTAT

    0x000b                                          0x0001000b       (POST boot is good)

    0x082b                                          0x00010021       (Nand boot is bad, expected 0x0001082b)

    The difference between the two as I understand is accessing the nand flash. So if the DSP doesnt like the nand flash during boot, could it throw away the boot mode pins status and not latch in the DEVSTAT?

    The boot mode pins status is set by an onboard FPGA (XC6SLX25T), same connections as the evm. The firmware is however our own, developed step by step through the device and evm documentation as we brought the custom board up. Is there more the evm FPGA does at power on/full reset for nand boot, than just setting the boot mode pins status?

     

    Many thanks,

    Tahir

     

  • 0 in reply to M Imran Tahir
    TI__Guru** 114410 points

    C6678 doesn`t support NAND boot in ROM bootloader so the NAND boot mode is supported through secondary bootloader (IBL) on the I2C. Latching of DEVSTAT occurs only during reset so I don`t think the DSP is throwing away boot mode pins status. Are you using the same IBL binary provided in the MCSDK or have you modified it ? Are you sure that there is no issues with the FPGA firmware that is connecting the GPIO pins to the boot pins. I will need to confirm but I think the FPGA firmware also applies reset to the NAND device.

    I will check with some hardware experts on details of FPGA firmware and get back to you.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 50 points

    Rahul,

    The ibl binary I had to modify as the DDR our custom board wouldnt run with 1.3GHz clock so had to reduce it to 1GHz for the DDR to work. It's same chip though as the evm. I tested the modified ibl with the evm and it worked fine for nand boot and expected values in DDR3PLLCTL0 register.

    We have a separate check on FPGA pins status that connect to boot mode GPIOs and it looks ok.

    At power on reset of the DSP the boot mode pins are held in tri-state by the FPGA. It then asserts reset full with the 082b vector on boot mode pins. Could that be an issue too that DSP must see 082b vector at power on reset as well?

     

    Many thanks,

    Tahir

  • 0 in reply to M Imran Tahir
    Prodigy 50 points

    The issue is now resolved.

     After some debugging found out that some EVM FPGA specific functions in ibl code were causing the problem.  In ibl\src\device\c66x\target.h,  un-defining IBL_ENTER_ROM  and  IBL_ENABLE_PCIE_WORKAROUND did the trick. The board now boots from Nand flash fine.

    Many thanks for all the help.

    Tahir

  • 0 in reply to M Imran Tahir
    TI__Guru* 81335 points

    Hi Tahir,

    Thank you very much for the update. I hope this would help many users.