C6655 Boundary Scan Help

The Data Manual contains basic information about the IEEE1149.1 JTAG port in section 7.27.3 copied below.  The BSDL model file also lists the compliance-enable pins RESETFULLz and PORz.  Power sequencing in the Data Manual in section 7.2.1 must be followed.  The clock sequencing is not needed for boundary scan testing since the state of the internal logic is irrelevent for BSCAN testing.  The RESETFULLz and PORz pins must be low during power ramp and then they must be high to allow BSCAN to function.

7.27.3 IEEE 1149.1 JTAG

The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes (SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).

7.27.3.1 IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6655/57 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high.  However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

Tom