This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Keystone II SRIO interface with FPGA and SerDes Configuration Datasheet

Other Parts Discussed in Thread: 66AK2H12

Hello all!

I'm trying to set up  SRIO interface between custom PCB with 66AKH12 ARM prosessor and FPGA. We are using srio kernel driver keystone_rio.c from TI's github:https://git.ti.com/keystone-linux/linux/blobs/9034d63c8cb90ec99f445d84fb9431d688541c69/drivers/rapidio/devices/keystone_rio.c.

Driver works fine in loopback mode and ports get enumerated.

When we connect FPGA and ARM, we can see from both's  port control and lane status registers that lane_sync works but can not get port enumeration.

I have tried to find serdes configuration manual for Keystone 2 SRIO. From 66AK2H12 manual I see that SRIO Serdes Config adresses are form 0x232c000 to 0x232DFFF but no information how to configuration can be done. For example in the driver there is a lot of set up's that i would like to understand: function k2_rio_serdes_init_5g() in line 1111 writes data in many offsets that are not clear for me.

Is there somewhere available SRIO SerDes configuration datasheet where is register definitons? Just to make sure that set up is correct for our purposes.

 br,


jv