Problem configuring aif2 RT module

Hi,

'pe_ee_rt_if_err' means the RT FIFO is overflowed by incoming stream from RM which means the Pe offset for the egress link was too late.

our RT FIFO size is fully large enough  to hold certain amount of incoming frame data until the egress DMA data is ready. if your PE1 and PE2 offset bigger than the RT FIFO threshold, you will see this error.

you can solve this issue by reducing the amount of PE1,PE2 and Delta offset on egress and the TM status problem also will be cleared once this timing issue is corrected.

Regards,

Albert   

Hello Albert,

The issue referred in my above post originates from the following scenario -

a. On TCI6670 board ,LINK 1 is a common link between DSP0 and DSP1
b. We are trying to implement external redirection in our code.
c. DSP0 Link 1 sends data on DSP1 LINK1
d. DSP1 Link 1 redirects its data on DSP1 LINK4
e. Aif2 serdes loopback is configured for DSP1 LINK4
f. DSP1 LINK4 receive is then redirected to DSP1 LINK1 Transmit
g. DSP1 LINK1 data is further recieved by DSP0 LINK1 for TX-RX data verification.

1. DSP0 sends/receives its data on LINK1 with following TX/RX timing ->
PE1 offset = 300
PE2 offset = 310
TM/Delta offset = 380
PIMIN = 380

2. DSP1 receives/sends DSP0 data on LINK1 with following TX/RX timing
PE1 offset = 300
PE2 offset = 310
TM/Delta offset = 380
PIMIN = 380

Observation->
1. DSP 0(Sender) LINK 1 TM status => CSL_AIF2_TM_ST_FRAME_SYNC (Correct!)
                        RM status => CSL_AIF2_RM_ST_0(Wrong!)

2. DSP 1(Receiver) LINK 1 RM status => CSL_AIF2_RM_ST_0(Wrong!)
                         TM status =>CSL_AIF2_TM_ST_FRAME_SYNC (Correct!)

Problem-      
The error mentioned above i.e.pe_ee_rt_if_err = 1 and tmFrameStatus = 4 are on LINK4. This is nothing but contains redirected data from DSP1 LINK1.
So,the actual error originated at Receiver of DSP1 LINK1(direct-link between DSP0 and DSP1)-Marked red!
 
Please suggest what could be the possible issue with our configuration,or do you see any problem in our understanding?

Regards,
Jeanne

Hi Albert,

1. Both DSPs are using the common AIF2 reference clock. 

2. Also,When DSP0 and DSP1 are using common ref clock, we have observed that DSP0 LINK1 serdes loopback as well as DSP1 LINK 1 serdes loopback are independently working correctly.(LINK1 being the direct or common link between DSP0 and DSP1)

3. Regarding the LINK 1 RM status i.e. for the case mentioned in my previous post, "  DSP 1(Receiver) LINK 1 RM status => CSL_AIF2_RM_ST_0(Wrong!) " -

a. Despite the correct TX-RX timings set(please refer below configuration),the Pi capture register mostly shows the Pi value as 0. Why it's 0 despite being correctly configured? 

    ----------------------------------------------------------------------

1. DSP0 sends/receives its data on LINK1 with following TX/RX timing ->
PE1 offset = 300
PE2 offset = 310
TM/Delta offset = 380
PIMIN = 380

2. DSP1 receives/sends DSP0 data on LINK1 with following TX/RX timing
PE1 offset = 300
PE2 offset = 310
TM/Delta offset = 380
PIMIN = 380

---------------------------------------------------------------------------------------------------

b. Moreover, In addition to  RM status as => CSL_AIF2_RM_ST_0(resync state), los bit = 1 always. What is the exact inference of this error scenario?

Please guide us in this issue and let us know if something is unclarified.

Regards,

Jeanne

Pi = 0 and LOS = 1 means there is physical level problem between two DSPs. It could be board design level issue or PCB design issue or SERDES configuration issue (if you changed SERDES config). your HW should check SERDES input signal if it shows clear eye view or not.

Regards,

Albert