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66AK2H main and DDR3 PLL frequency

UNA
Mastermind 7980 points
Other Parts Discussed in Thread: 66AK2H12

Hi,

I have questions about main PLL and DDR PLL on 66AK2H12/06.
Please refer to the following figure. It is an excerpt from the data sheet(SPRS866E).


1. Does PLLD output of main PLL (at point A) has constraints of frequency range ?

2. Does VCO output of main PLL (at point B) has constraints of frequency range ?

3. Does PLLD output of DDR3 PLL (at point C) has constraints of frequency range ?

4. Does VCO output of DDR3 PLL (at point D) has constraints of frequency range ?


Best regard
H.U

  • 0
    TI__Mastermind 43660 points

    Hello H.U,

    The PLLM is a 13 bit field which has a multiplication factor up to 8192. The PLLD is a 6 bit field which has a division factor up to 64. This is applicable for both main PLL and DDR3 PLL.

    Though there is no limitation on setting the multiplication and division factor, it is indirectly limited by the core operating frequency and DDR3 operating frequency.

    The maximum core operating frequency (SYSCLK1) is 1.4 GHz and the PLLM, PLLD and POSTDIV register values has to be set in such a way that SYSCLK1 does not exceed the maximum rating.

    The maximum DDR3 clock frequency is 800 MHz and the DDR3 PHY has fixed multiplier of 2. So the maximum DDR3 PLLOUT frequency is limited to 400 MHz. The DDR3 PLLM and PLLD register values has to be set based on this maximum rating.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Mastermind 7980 points

    Hello,  SenthilKumar,

    Thank you for your quick reply. 
    I understand PLLs configuration.

    Best regards,
    H.U

  • 0 in reply to UNA
    Mastermind 7980 points

    Hello,  SenthilKumar,

    I have a little more question.

    You say there is no limit to the PLL multiplication and division setting.
    So, I think that PLLD output is also no problem even if there is less than 1Mhz by increasing the division ratio.
    Is my thinking correct?

    Best regards,
    H.U

  • 0 in reply to UNA
    TI__Mastermind 43660 points

    Hello H.U,

    Yes, your thinking is absolutely correct. 

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    TI__Mastermind 43660 points

    Hello H.U,

    I got an update on this from the design team. With respect to the PLL spec, please find below the recommendations on PLL range.

    1. There are max and min VCO frequency values. The operational frequency range for the VCO should be 700MHz – 4000MHz. Just to clear, this VCO frequency is equivalent to the frequency out of the PLL multiplier (PLLM). There is no minimum and maximum on the PLL output frequency.

    2. In order to minimize jitter, a user should be guided to maximize the VCO frequency using the multiplier and then divide down to the desired output using the OD. In general, the higher the VCO frequency the lower the jitter.

    3. The above recommendations apply to Main, DDR and NETCP/PA PLLs.

    Regards,

    Senthil