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C66xx DDR3 Issues

Other Parts Discussed in Thread: TMS320C6678

Hi All,

We have designed a Quad Processor Board( '4' DSP Processor TMS320C6678), We have followed the Length Matching Constraints.DDR3 Chip we are using is MT41K128M16 - Vendor MICRON, Size 1GB.

Our Board Design consist of 72-bit (64-bit plus ECC) single-rank DDR3 DRAM topology using x16 DRAMs.  For DSP1, DSP2, DSP4 the DDR3 is Working Fine.

But For DSP3 We can't able to access even a single DDR3 locations. 

I have also Attached the DDR3 PHY Calc v10.xsl and DDR3 Register Calc v4.xls of DSP3. 

I Have also attached the Memory Browser screen shot before and after accessing the DDR3.

Before Acessing DDR3:

  

After Accessing DDR3:

0624.DSP-3.xlsx

7888.DDR3 Register Calc v4.xls

What Can be an issue.

Can any one provide ideas or suggestion for this issues. Thanks in Advance.

Regards ,

Avinash N

  • Dear Sir/Madam,

    Another Updates ,

    i) DDR3 Memory Controller Status Register -- 0x21000004(Address)   ---------   0x40000004 (DSP1,2,4).

    ii) DDR3 Memory Controller Status Register -- 0x21000004(Address)   ---------   0x40000074 (DSP3).

    From the Status register we can come to know that the below section is set for the Failing DSP & DDR3 Combination.

    a) Read DQS Gate Training Timeout

    b) Read Data Eye Training Timeout

    c) Write Leveling Timeout

    Question:

    What can be the issue.

    Any help from TI Side.

    It is very urgent. Kindly provide the support.

    Regards,

    Avinash N 

  • Hello Avinash,

    The similar issue is already addressed in below thread. You can find some suggestions to fix this problem.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/245248/858179.aspx

    Regards,

    Senthil

  • Hi Senthi,

    We have followed the Constrains provided in the TI recommendation. Can you provide any ideas why we can't able to access even a single Bit out of 64bit. Can you take a look at the memory browser screen shot For reference.

    Regards,

    Avinash N

  • Avinash,

    Are the routed lengths for all 4 DSPs identical?  Please provide spreadsheets or reports showing the routed lengths for all 4 DSPs including proof that the routing rules have been followed.  Then provide the corresponding PHY_CALC spreadsheets that you used to generate the INIT_LVL values used in the initialization routine.

    Tom

     

  • Hi Tom,

    Thanks For the Reply.

    The Routing Length for all the 4 DSP(TMS320C6678CYPA1.25) are identical.

    I have attache the Following File for your reference,

    a) PhyCalculated_SpreadSheet_DSP3.rar (For 3rd DSP).

    b) RoutingLenth-DSP(TMS320C6678CYPA1.25).rar ( For All the 4 - DSP's).

    c) Routing-Proof_Followed.rar (For 3rd DSP)

    3833.PhyCalculated_SpreadSheet_DSP3.rar

    1004.RoutingLenth-DSP(TMS320C6678CYPA1.25).rar

    4265.Routing-Proof_Followed.rar

    Constraints followed from the Document sprabi1b.pdf. I have attached the Document sprabi1b.pdf and highlight the rules we followed in GREEN Color and the query in Orange Color.

    2043.sprabi1b.pdf

    In status Register the following bits are SET For DSP3 (Non Working)

    a) RDLVGATETO

    b) RDLVLTO

    c) WRLVLTO

    d) IFRDY

    But the above a, b & c  are not SET For DSP1, DSP2, DSP4 (Working).

    Question:

    1. What can be the issue cause?

    2. This sort of issue is because Software Register Configuration or any thing else?

    Regards,

    Avinash N

  • Avinash,

    Hardware layout and SDRAM selection and software implementation are all closely coupled.  Any or a combination can cause failure.  Success occurs only when all are properly aligned.  The status bits reported are basically telly you that leveling is failing to complete on this DSP.  Either the layout or the programming has a problem.  Since you have 4 interfaces functional and one completely failing, have you reverified you schematic to make sure there are no errors.

    The layout information provided is incomplete.  You show DQS and CLK pair routing for each DSP subsystem.  This looks good.  It also shows that the 4 SDRAM layouts are not identical.  You provided a report in DDR3_Rules_DLRL(3).XLS for one of the DSPs.  This is needed for all 4.  Then you need to provide the completed PHY_CALC worksheets for all 4 DSPs.

    Tom

     

  • Hi Tom,

    I have attached the PHY_CALC Worksheet for all 4 DSPs.

    3755.DSP-1.xlsx

    7802.DSP-2.xlsx

    6366.DSP-4.xlsx

    Any solution for the above issue?

    Regards,

    Avinash N

  • Avinash,

    You provided a report in DDR3_Rules_DLRL(3).XLS for one of the DSPs.  This is needed for all 4.

    Tom

     

  • Avinash,

    The PHY_CALC worksheets align correctly with the DQS and CLK lengths reported in the LengthMatch sheets.  Did you modify a GEL file with these configuration settings?  If not, please take the standard GEL delivered with CCS for the C6678 and modify it with your computed PHY_INT settings.  Start with one of the working subsytems.  You will also need the calculated register setting from the REG_CALC spreadsheet.  Please also add that worksheet to this thread.  Once you have verified that the GEL passes on a known good subsystem, make a different version for the failing subsystem and verify that you see the same failure mode reported above.  This is a very useful validation step since the GEL avoids common programming issues that often cause customers to have DDR3 configuration problems.  Also, there is a simple DDR3 memory test in the GEL that can be used to diagnose DDR3 failures.

    Tom

     

  • Hi Tom,

    Yes I have modified the GEL File with the PHY_CALC values. We are using the Standard GEL File(evm6678.gel) for the Customized board. We have reconfigured the PLL and other settings as required.

    In the GEL File For DDR3 Configuration section FOR DSP1, DSP2,DSP3 and DSP4 the timing Values remain the same as the DDR3 Capacity 1GB for each DSP.  Only the Length Matching Values are different For every DSP Processor.

    I have attach the GEL File For your Reference.

    8664.DSP3.gel

    The Simple DDR3 memory test gets Failed.

    We can't able to write/read even a single bit out of 64bit.

    Regards,

    Avinash N

  • Avinash,

    You provided a report in DDR3_Rules_DLRL(3).XLS for one of the DSPs.  This is needed for all 4.

    This hard failure for a single subsystem where all bits fail does not sound like a marginal configuration issue.  I think this sounds like a schematic / connection error.

    Please also provide your REG_CALC worksheet.

    Tom

     

  • Hi Tom,

    I have attached the DDR3_Rules_DSP(1), DDR3_Rules_DSP(2), DDR3_Rules_DSP(3) & DDR3_Rules_DSP(4).

    2311.DDR3_Rules.rar

    Thanks for your immediate response.

    Regards,

    Avinash N

  • Hi Tom,

    I have attached theDDR3_Rules_DSP(1),DDR3_Rules_DSP(2),DDR3_Rules_DSP(3) &DDR3_Rules_DSP(4) along with the REG_CALC worksheet.

    0246.DDR3_Rules.rar

    3324.DLRL-DDR3 Register Calc v4.xls

    Thanks for your immediate response. Waiting for your reply.

    Regards,

    Avinash N

     

  • Avinash,

    I have verified the 4 'length match' worksheets are correct and match up with the 4 'rules' worksheets.  I then verified that the lengths are all implemented correctly into the 4 PHY_CALC 'dsp' worksheets.  However, i noticed that the 'dsp' worksheets for #1, #2 and #4 indicate a DDR clock rate of 800MHz.  At this time, the C6678 does not support 1600MT/s.  Please see Usage Note 14 in the C6678 Silicon Errata document SPRZ334.  Values must be pulled from these worksheets with the proper clock rate.  Please provide corrected worksheets.

    You provided a single REG_CALC worksheet.  However, this worksheet has been hacked.  We will not review this as it is too difficult to look for spreadsheet errors.  If you want your settings reviewed, you must properly populate a new one of the web that has not been broken.

    Tom

     

  • Hi Tom,

                  Sorry For the Delay reply. We are under Full pressure Regarding DSP3 DDR3 Accessing .  Can you refer to the bellow post http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/383169/1350992.aspx#1350992. Because our DSP3 is also placed near the Power Module. We have Manufactured Another board. In that also the same problem.

    Is there any possiblity to check whether DDR_PHY ?

    Is there any other possibility to Prove that DDR3 Memory Controller Configuration is correct ?

    8407.DDR3 Register Calc v4.xlsx

    Can you provide any response. It is very urgent ?

    Thanks in Advance.

    Regards,

    Avinash N

  • Avinash,

    You are saying that you manufactured another board and it fails the same.  How many boards in the first batch and how many in the second batch?  Do 3 DDR3 subsystems work on all boards and the one on DSP-3 always fails the same way?

    The problem that you are describing does not appear to be a marginal register configuration.  You need to be looking for something more fundamental.  Did you verify the 1.5V supply to the SDRAMs and DSP PHY for the failing subsystem?  Similarly, did you verify DDR3CLKOUT to the SDRAMs on this subsystem.  Has the VREF to all locations been checked as well as the VTT term for this subsystem?

    I previously suggested that you verify the schematic and routing to look for a connection error.  Has this been done?

    You have mentioned that this DDR3 subsystem is close to a power converter.  You are concerned that this might be causing the problem.  You should disable this power supply and then supply the voltage from a lab bench supply.  You can even inject this voltage at a different location on the board to prevent the ground and supply currents flowing near the DDR3 layout.  Please let me know whether this changes the problem.

    Tom

     

  • Hi Tom,

    We will check with your points and we will get back to you.

    Regards,

    Avinash N

  • Hi Tom,

    Updates Regarding the Issue,

    Across VTT we have replaced 10uf Tantalum capacitor by 10uF ceramic capacitor (6no's) and added 100uF capacitor across 1.5V as recommended by TI.
    After Making the Above changes we can able to access the 64bit.

    But Still we are facing issues as mentioned bellow:
    From GEL File OBSERVATION:

    we are trying partial auto leveling concept. We have made around 6 GEL files. Such as Clock and Bit: (666.66 & 64), (666.66 & 32), (533 & 64), (533 &32), (400 & 64) and (400 &32).
    Miscount - Number of mismatch between writing and reading a known pattern(0xA5A5A5A5).

    Miscount For 64Bit,
    400 MHz Clock - aprox  962609
    533 MHz Clock - aprox  1063545
    666.666MHZ Clock -  aprox  1237682

    Miscount For 32Bit,
    400 MHz Clock - aprox  50
    533 MHz Clock - aprox  850
    666.666MHZ Clock -  aprox  1000

    The Miscount occur in random location.
    We observed read cycles are not proper as consecutive read's on same memory location gives different values.

    We have also attached the ODT screen shot for working DSP and Non Working Screen DSP for your reference.

    Non Working DSP - ODT Signal:
    Working DSP - ODT Signal:

    Regards,
    Avinash N


  • Avinash,

    When you indicate 'working' and 'non-working' in the previous post and pictures, I assume that you mean:

    • Working - DSP #1, #2 and #4 on all boards
    • Non-working - DSP #3 on all boards

    Is this correct?  I have asked questions like this before and you have not answered them.  I cannot help you debug your board if you do not answer my questions.  I need answers to all of my questions in the 11/27 post.

    You mention that reads are unstable if you read them multiple times.  reading them with a CCS memory window will not show the failure pattern correctly.  You should read a single failing location multiple times using a CCS GEL file or C-code to get a clear understanding of the read failure pattern.  Please provide this as it will help me understand your problem.

    How does this unstable read issue compare to the previous hard failure?  Are you saying that addition of the decoupling capacitors made that much improvement.  This makes me believe that the layout is not robust.  Please provide a layer stack-up that indicates which signal and planes are on which layers - specifically in the region reserved solely for the DDR3 routes.

    Tom

     

  • Hi Tom,

    When you indicate 'working' and 'non-working' in the previous post and pictures, I assume that you mean:

    • Working - DSP #1, #2 and #4 on all boards
    • Non-working - DSP #3 on all boards

    Is this correct?

    Yes.

    You mention that reads are unstable if you read them multiple times.

    We have tested in two cases,

    1. Single Write with a pattern and five times read and compare with that pattern entire 1GB.

    2. Five times write different pattern and read and compare with that pattern entire 1GB.

    We are currently checking using the C code not the CCS Browser.

    How does this unstable read issue compare to the previous hard failure?  Are you saying that addition of the decoupling capacitors made that much improvement .

    Yes. After making the below changes we can able to access.

    Across VTT we have replaced 10uf Tantalum capacitor by 10uF ceramic capacitor (6no's) and added 100uF capacitor across 1.5V as recommended by TI. Added 10ohm across 1.5V and ground .

    Please provide a layer stack-up that indicates which signal and planes are on which layers - specifically in the region reserved solely for the DDR3 routes.

    Layer1 - TOP      

    Layer2 - PLANE     Ground

    Layer3 - SIGNAL      

    Layer4 - PLANE       1V

    Layer5 - SIGNAL     DDR Signal

    Layer6 - PLANE       Ground

    Layer7 - SIGNAL     DDR Signal

    Layer8 - PLANE       Ground/ Power

    Layer9 - SIGNAL     DDR Signal

    Layer10- PLANE       3.3V

    Layer11- SIGNAL     DDR Signal

    Layer12- PLANE     Ground

    Layer13- SIGNAL

    Layer14- SIGNAL      

    Layer15- PLANE     Ground

    Layer16- SIGNAL      

    Layer17- PLANE     Power

    Layer18- SIGNAL     DDR Signal  

    Layer19- PLANE       Ground / Power

    Layer20- SIGNAL     DDR Signal

    Layer21- PLANE       Ground / Power

    Layer22- SIGNAL     DDR Signal

    Layer23- PLA

    Regards,

    Avinash N

  • Avinash.

    Since you indicate that adding decoupling changes the behavior, this indicates the layout is marginal.  Also, the improper waveforms for the ODT indicate crosstalk or reference plane issues.  Additionally, the stack-up does not provide confidence since you are routing DDR on 7 different layers and this is only a 32/36-bit interface.  Please provide PDF images of the DDR3 layout area showing all 24 layers.

    Have you tested with an external supply such that the nearby supply is disabled?  Make sure that you attached the external supply at a different location to prevent large ripple currents near the 3rd DSP.  You can attach at a large decoupling capacitor near the load.

    Tom

     

  • Hi Tom,

    Since you indicate that adding decoupling changes the behavior, this indicates the layout is marginal.

    We are using the decoupling capacitor as per the TI Recommendation.

    Have you tested with an external supply such that the nearby supply is disabled?

    Yes we have tested with an external supply such that the near by supply is disabled. In that scenario the case becomes worse. The miscount is increased to 450MB.

    Please provide PDF images of the DDR3 layout area showing all 24 layers.

    Along with this mail I have attached the PDF Image of all 24 layers.

    Layer1 - TOP      

    Layer2 - PLANE     Ground

    Layer3 - SIGNAL      

    Layer4 - PLANE       1V

    Layer5 - SIGNAL     DDR Signal

    Layer6 - PLANE       Ground

    Layer7 - SIGNAL     DDR Signal

    Layer8 - PLANE       Ground/ Power

    Layer9 - SIGNAL     DDR Signal

    Layer10- PLANE       3.3V

    Layer11- SIGNAL     DDR Signal

    Layer12- PLANE     Ground

    Layer13- SIGNAL

    Layer14- SIGNAL      

    Layer15- PLANE     Ground

    Layer16- SIGNAL      

    Layer17- PLANE     Power

    Layer18- SIGNAL     DDR Signal  

    Layer19- PLANE       Ground / Power

    Layer20- SIGNAL     DDR Signal

    Layer21- PLANE       Ground / Power

    Layer22- SIGNAL     DDR Signal

    Layer23- PLA

    Vtt – Bottom Solid Plane

    Vref – Layer 15Mil Trace

    Layers:

    L20 Data

    L18 Address

    L16   DQS

    L11   Clock

    L9   Address / Data

    L7   Address / Data

    L5   Data

    Regards,

    Avinash N

     

  • Hi Tom,

    Sorry In Last Mail i have Forgotten to attach the Layer Details, and In TI Forum I can't able to attach the .zip file. Can you provide any other Id.

    Avinash N

  • Avinash,

    The E2E has been changed.  You should be able to attach files by clicking on the Insert Media button and then selecting File.

    Tom

     

  • Hi Tom,

    Since you indicate that adding decoupling changes the behavior, this indicates the layout is marginal.

    We are using the decoupling capacitor as per the TI Recommendation.

    Have you tested with an external supply such that the nearby supply is disabled?

    Yes we have tested with an external supply such that the near by supply is disabled. In that scenario the case becomes worse. The miscount is increased to 450MB.

    Please provide PDF images of the DDR3 layout area showing all 24 layers.

    Along with this mail I have attached the PDF Image of all 24 layers.

    Layer1 - TOP      

    Layer2 - PLANE     Ground

    Layer3 - SIGNAL      

    Layer4 - PLANE       1V

    Layer5 - SIGNAL     DDR Signal (Data)

    Layer6 - PLANE       Ground

    Layer7 - SIGNAL     DDR Signal (Address/Data)

    Layer8 - PLANE       Ground/ Power

    Layer9 - SIGNAL     DDR Signal (Address/Data)

    Layer10- PLANE       3.3V

    Layer11- SIGNAL     DDR Signal (Clock)

    Layer12- PLANE     Ground

    Layer13- SIGNAL

    Layer14- SIGNAL      

    Layer15- PLANE     Ground

    Layer16- SIGNAL   DDR Signal (DQS)  

    Layer17- PLANE     Power

    Layer18- SIGNAL     DDR Signal(Address)  

    Layer19- PLANE       Ground / Power

    Layer20- SIGNAL     DDR Signal(Data)

    Layer21- PLANE       Ground / Power

    Layer22- SIGNAL     DDR Signal

    Layer23- PLA

    Layer24-Bottom

    Layer24   - DQS / DDR Clock

    Layer25  -   Plane

    Layer26  -  Bottom

    DDR3_Layers.rar

    Vtt – Bottom Solid Plane

    Vref – Layer 15Mil Trace

    I Have added the remaining layers in the next consecutive mail.

    Regards,

    Avinash N

  • Hi Tom,

    As the Size of the overall file is 40 MB therefore i have splitted in to three files. They are,

    1. DDR3_Layers.rar

    2. OtherLayers_1.rar

    3. Other_Layers_2.rarOtherLayers_1.rar

    Regards,

    Avinash N

  • Hi Tom,

    I have attached the remaining Layers File Along with this mail.

    Other_Layers_2.rar

    Regards,

    Avinash N