PCIe Boot

Hi Roee,

PCIe Boot example is available in MCSDK package. Please take a look at below document and example code.

Document: \ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\docs\README.pdf

PCIe Code: \ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader/pciedemo.c

Refer HELLO_WORLD_DEMO code part in pciedemo.c file. Hello world demo required DDR initialization.

#if HELLO_WORLD_DEMO
		/* Load DDR init code into DSP */
		pushData(ddrInitCode, 0, &bootEntryAddr);

		/* Write boot entry address into MAGIC_ADDR */
		writeDSPMemory(0, MAGIC_ADDR, &bootEntryAddr, 4);       

		while (1) {
			readDSPMemory(0, MAGIC_ADDR, buffer, 4);
			if (buffer[0] == 0)  break;
			for (i = 0; i < 1000; i++) i++;
		} 

		/* Load "Hello World" demo into DSP */
		pushData(bootCode, 9, &bootEntryAddr);

		/* Write boot entry address into MAGIC_ADDR */
		writeDSPMemory(0, MAGIC_ADDR, &bootEntryAddr, 4);
#endif

Thanks,

I'm familiar with that example.

I'm loading the DDR example and the DDR is successfully initialized and I can write into it via one of the PCIe bars from my PC.

After initializing the DDR with the program above, I load my program (not the hello world example) and set the magic address to 0x80000 which is the start address for my program.

After that nothing happens tho I can see the the entry point is updated but there is no jump.

Hi,

the local L2 address is not 0x80000 (as in your post) but 0x800000. You're missing one zero ...

Kind regards,

one and zero

That was a typing error here.

I've attached the last 4 bytes of the binary file I've loaded to L2 Core 0.

0x800000 is written to the magic address as part of the binary image (it is 1 Mb, as the size of L2 Core 0)

but the IBL doesn't make the jump.

That was a typing error.

I've attached the binary file I'm loading into L2 Core 0.

The size of the binary is 1 MB, the same as L2 Core 0.

I'm loading the file successfully via PCIe, and last 4 bytes are 0x800000 are written to the magic address 0x008FFFFC but the IBL does not make the jump.

I don't want to use interrupts.

I want the same scenario as in the hello world example following the DDR init, because I'm using the DDR.

Hi,

Please share your binary file. I will try to reproduce your issue.

Thanks,

Sure, what is your email?

Please attach your binary file with .zip format.

Hi

I have a problem attaching it here, can I send it to you directly ?

2677.firmware.zip

I've attached the binary file.

Please check if you can boot with it via PCIe.

Thanks

I've just realized that in the pci boot hello world example one must load the application image to the DDR memory and not the L2 Core 0 memory.

I want to load and run my application from L2 Core 0 and not DDR.

In the PCIe boot hello world example it states:

"The Linux host first pushes the DDR init boot image data to L2 memory of core 0, then writes the boot entry address of the DDR init boot image to the magic address on core 0, both via PCIE. When the EVM is in PCIE boot mode, the IBL code running on the DSP core 0 polls the entry address and jumps to that address and starts to boot (initialize the DDR). After DDR is properly initialized, the DDR init code clears the magic address and keeps on polling it. Linux host then pushes the HelloWorld boot image data to DDR memory, then writes the boot entry address of the HelloWorld boot image to the magic address on core 0 to boot core 0. Core 0 starts to boot and print the “Hello World” booting information, and then boot all the other cores by writing the address of _c_int00 to the magic address on other cores and sending an IPC interrupt to other cores. The RBL running on other cores will jump to _c_int00 and start to boot, each core will write 0xBABEFACE to its magic address by running a function write_boot_magic_number()."

Because it says "then writes the boot entry address of the HelloWorld boot image to the magic address on core 0 to boot core 0" , I'm a bit confused.

Is it not running from DDR?

Hopefully you can help to clarify that, thanks.

Hi,

In PCIe boot Hello world example running in DDR memory that only user need to load DDR init code image to L2 memory and initialize the DDR memory and then Load the Hellow world immage to DDR memory.

In your case you can directly load your image to L2 memory. Please refer POST_DEMO code part in pciedemo.c file.

Thanks,

Could you please attach the pcieboot_post project.

Seems all I have is the pcieboot_post.h but no pcieboot_post..c file.

I have another post project but that one boots from I2C.

Thanks

Hi,

For boot via PCI I'm using IBL.

As far as I know using an interrupt for booting via PCI is needed when using the RBL,

Am I correct?

Yes, Your understanting is correct.

Thanks,