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SPI CLK during Boot

Andreas_RS
Prodigy 50 points

Hello Senthil,

Following this thread, I do understand, that the SPI shall be used for DSP boot purposes. From the documentation I gathered, that during SPI boot the PLL is set into Bypass mode by RBL, which means

CoreClk / 6 = SysClk7;

312.5 MHz / 6 = 52.08 MHz;

which also is the SPI Module clock. Latter is further divided down by the Prescaler which is initially set to zero. A zero means div 2, resulting in a SPI Clock rate of 26.04 MHz.

Q1) Is the statement about PLL Bypass Mode correct?

The documentation also says the minimum period for SCK is 3*P2, resulting in a maximum allowed SPI-Frequency of 17.36 MHz. Apparently, this maximum rating is exceeded by simply having the BOOTMODE Pins set to SPI-boot in conjunction with the fastest XCO at CoreClk Input.

Q2) Is 17.36 MHz really the physical limit of the DSP device / SPI subsystem? Many SPI-Flash Memories already allow operation at 80 MHz or 100 MHz to date.

Q3) Why is a physical constraint (here: 1/f(SCK) = 3*P2) denoted in dependency of the XCO Input Frequency (CORECLK P|N), shouldn't it be a fixed indication stated in nanoseconds?

Q4) How can one set the Prescale value to an allowed range when initially booting only with the information provided at the BOOTMODE pins?

When booting from I2C or SPI, the BOOTMODE uses 10 bits (12:3) instead of 7 bits (9:3). The bits (12:10) normally are used to configure the PLL.

Q5) In I2C or SPI Boot are those bits (12:10) overrided / just taken for boot config and not for PLL config?

If the PLL is in Bypass, then it seems that the Cores rather run at the slower Input clock (312.5 MHz) than on the final device clock at 850/1000/1250 MHz.

Q6) Is this correct? Is an additional PLL configuration needed at a later stage?

 

Thank you for your help,

Andreas

  • 0
    TI__Mastermind 43660 points

    Hello Andreas,

    For better followup, your query is moved to a new thread.

    Following this thread, I do understand, that the SPI shall be used for DSP boot purposes. From the documentation I gathered, that during SPI boot the PLL is set into Bypass mode by RBL, which means

    CoreClk / 6 = SysClk7;

    312.5 MHz / 6 = 52.08 MHz;

    which also is the SPI Module clock. Latter is further divided down by the Prescaler which is initially set to zero. A zero means div 2, resulting in a SPI Clock rate of 26.04 MHz.

    Yes, your understanding is correct. The above mentioned SPI clock rate is applicable before SPI initialization.

    A1) The RBL must performs SPI initialization before accessing the SPI device for boot purpose. During SPI initialization, the PRESCALE register value will be set in such a way that it is within the specified limit. At any point of time, the SPI device cannot be accessed without prescaled clock.

    A2) The maximum SPI clock is wholly depends on the core operating frequency. For example, if you operate the core at 1200 MHz, the SYSCLK7 will be 200 MHz. In this case, the maximum SPI clock will be 66.67 MHz.

    A3) Since the SPI module clock is derived from the XCO input clock, the physical constraint is set dependent on the CORECLK P/N. The unit is still defined in nano seconds only.

    A4) Refer A1.

    A5) Yes, the bits [12:10] are used for boot config in I2C or SPI mode. The device will be operated at lower frequency (input clock) in bypass mode.

    A6) No additional configuration is required.

    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 50 points

    Hello Senthil,

    Thank you for the answers to my questions.

    RE1)

    The above mentioned SPI clock rate is applicable before SPI initialization.

    The RBL must performs SPI initialization before accessing the SPI device for boot purpose

    I further studied the behaviour of the ROM-Boot-Loader. Since RBL is being executed immediately after /POR + /RESETFULL + BOOTMODE pins, the previously mentioned SPI Clock Rate of 26.04 MHz does not apply in operation. Instead RBL configures the PRESCALE register to 33'dec (21'hex), assuming an input frequency at CORECLK of 100 MHz and targeting a SPI frequency of 505 kHz.

    Since the assumption of 100Mhz is made, but we actually operate the device at 312.5 MHz, the SPI Clock will be 1.578 MHz instead. So, after this first boot sequence we will have to perform a secondary boot sequence, configuring the PLL in the desired way and using a Boot Parameter Table for Re-Initializing SPI to about 70 MHz, then reenter the boot again as described in the "TI Multicore Training - Keystone Boot Loader pptx" document for I2C.

     

    RE2) 

    The maximum SPI clock is wholly depends on the core operating frequency. For example, if you operate the core at 1200 MHz, the SYSCLK7 will be 200 MHz. In this case, the maximum SPI clock will be 66.67 MHz.

    Actually I was asking what is the toggling limit of the I/O Pins for that device. Thus, what is the maximum SPI rating that the device can accept since SPI is realized as a function of GPIO pins. Effectively, what PLL and PRESCALE I can enter to the Boot Parameter Table.

     

    RE5 / RE6)

    A5) Yes, the bits [12:10] are used for boot config in I2C or SPI mode. The device will be operated at lower frequency (input clock) in bypass mode.

    A6) No additional configuration is required.

    If the device comes up with 312.5 MHz @ SysClk1 (the frequencies for the CorePac's), then indeed there is a need to reconfigure the PLL to 850/1000/1250 MHz. Your statements in A5) and A6) are excluding each other, aren't they?

     

  • 0 in reply to Andreas_RS
    Prodigy 50 points

    Hello,

    By now I have verified the abovementioned findings getting the DSP to boot via SPI and using an Oscilloscope to measure the output frequencies.

    Since CORECLK is 312.5 MHz, SYSCLK7 and SYSCLKOUT are 52.08 MHz, the SPICLK is running at 1.57 MHz, which confirms that PRESCALE register is set to 32'dec by RBL, resulting in a divisor of 33'dec.

    This also means, the initial SPICLK frequency, that is set before RBL comes up does not apply in operation.

    It 'd be better if the datasheets clarify, that the given specifications for booting from BOOTMODE pins are only for the initial case and will be modified by RBL later on.

  • 0 in reply to Andreas_RS
    TI__Mastermind 43660 points

    Hello Andreas,

    Thanks for your update on this. It is supposed to work like you mentioned above.

    Anyhow we will make a note of it and update the datasheet by next version.

    Regards,

    Senthil