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66AK2H12 DDR3 register settings

UNA
Mastermind 7980 points
Other Parts Discussed in Thread: 66AK2H12

Hi, all,

I have questions about the following DDR3 registers of 66AK2H12.
Please tell me how to use it.

I check the DDR3 UG(SPRUHN7A) but can not understand the registers settings.
Do you have more detailed documentation of these registers?


- SDTIM2.T_RTW
  - dqs_delay_for_cs0 and dqs_delay_for_cs1 
  - command_delay_for_cs0 and command_delay_for_cs1
  - wr_leveling_tolerance

1. How do I derive the above values?


- SDTIM4.T_CSTA

2. How do I derive the above values?


- PGCR1.DLDLMT

3. How should I determine this value?


- PGCR1.FDEPTH

4. How should I determine this value?
5. What is the effects?


- PGCR1.LPFDEPTH

6. How should I determine this value?
7. What is the effects?


- PGCR1.MDLEN

8. What is the Master Delay Line?
9. What is the effects by this bit set to 1?


- PGCR1.WLSELT

10. How should I determine this value?


- PGCR1.WLSTEP

11. What is the difference of setting 32 step and 1 step.


- PGCR1.WLMODE

12. I think this bit field is to indicate whether it is Write Leveling Mode.
    So, I understand this is only used to read access, right?


- ZQnCR1.ZPROG

13. How should I determine this value?


- DXnGCR
 
14. I do not know what to set this register.
    Do you have more detailed documentation of each bit field?


Best regards,
H.U

  • 0
    TI__Mastermind 46460 points

    HU,

    Please see the attached spreadsheet tool that helps with the calculation of the register values.

    4137.K2 DDR3 Register Calc v1p51.xlsx

    The MCSDK package contains a GEL file for use with CCS that contains the programming steps and starting values.  Similarly, it contains example code in the PDK and sample Linux code for configuration the DDR3 interface.

    These configuration examples combined with the K2 DDR3 Controller UG and the attached spreadsheet should be sufficient for you to successfully configure the DDR3 controller and PHY.  We recommedn that you validate your board with the CCS GEL file prior to integrating it into your application code.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Guru 10570 points

    Hello, Tom.

    Thank you for infomation of the DDR Calc spreadsheet.
    In this sheet, following two parameters are needed to provide by user.

    - SDRIM2.T_RTW
    - SDRIM4.T_CSTA


    My question is:
      How can you decide these register value?

    Best regards, RY

  • 0 in reply to RY9983
    TI__Mastermind 46460 points

    RY,

    These are values that can be adjusted based on board design.  Both are discussed in the K2 DDR3 UG SPRUHN7A.  The spreadsheet is populated with conservative values that are known to result in robust operation on all boards.  These values must be used during initial functional validation of your board design.  Customers can then adjust these later as they choose based on the guidance in the K2 DDR3 UG.  Almost all customers leave them at the default values provided in the REG_CALC spreadsheet.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Guru 10570 points
    Hello, Tom.

    I can not find the guidance in the K2 DDR3 UG about these parameters.
    Can I have questions again?

    SDTIM2.T_RTW
    - dqs_delay_for_cs0 and dqs_delay_for_cs1
    - command_delay_for_cs0 and command_delay_for_cs1
    - wr_leveling_tolerance

    Q)
    What period do they specify?
    Do I have to measure the period in our target board?

    - SDTIM4.T_CSTA
    I am guessing I have to measure the write-to-write or read-to-read cycles in DDR3_CE0 and DDR3_CE1. Is that right?

    Q)
    When I use single rank DDR3 memory, I can set it default value or zero?
  • 0 in reply to RY9983
    TI__Mastermind 46460 points

    RY,

     

    RTW:

     

    The delays are board delays.  This can be gotten through simulation oe estimated from the trance lengths

    • dqs_delay_for_cs0 = DQ/DQS bus board delay for rank 0
    • dqs_delay_for_cs1 = DQ/DQS bus board delay for rank 1
    • cmd_delay_for_cs0 = command bus board delay for rank 0
    • cmd_delay_for_cs1 = command bus board delay for rank 1
    • wr_leveling_tolerance = margin to account for variations in all leveling modes - you can use 1/4 of the DDR clock period

    The calculation from Table 4-8 in the DDR3 Controller UG (SPRUHN7A) would have to be repeated for each byte lane and then the largest value chosen.  You need to validate your board design with the default value of 7 shown in the REG_CALC worksheet.  Later, this can be reduced to the value calculated during system tuning after the board design is already proven to be robust.

     

    CSTA:

     

    This is not a customer measured term.  The minimum value validated on the EVM is 5 as shown in the REG_CALC worksheet.  After you have validated robust operation of your board design, you may be able to reduce this setting to 4 or even 2.  Do not go below 2.

     

    Tom

     

     

  • 0 in reply to Tom Johnson 16214
    Guru 10570 points
    Tom,
    Thanks for your advise.

    CSTA:
    I can not understand what value is reliable for our system.
    To decide parameter, how can I do?

    Best regards, RY
  • 0 in reply to RY9983
    TI__Mastermind 46460 points

    RY,

    My initial recommednation as above it to leave it at the proven robust value of 5.  However, if you wish after your board is validated to operate DDR3 robustly, then you can also try the lower values of 4 and even 2.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 220 points

    Hi Tom,

    Is there a formal place where updated version of this spreadsheet file can be retrieved from (a web link outside of e2e)?

    BR, -Topi

    PS. The tZQCS settings for the following memory types is incorrect (should be fixed 64).

    K4B4G1646B (800) K4B4G1646B (1066) K4B4G1646B (1333) K4B4G1646B (1600)
    80 80 80 80
    max(64nCK, 80ns) max(64nCK, 80ns) max(64nCK, 80ns) max(64nCK, 80ns)
  • 0 in reply to Topi Rinkinen
    TI__Mastermind 43660 points

    Hello Topi,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    The latest DDR timing spreadsheet link is available in below KS2 DDR3 initialization guide.

    http://www.ti.com/lit/an/sprabx7/sprabx7.pdf

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    TI__Mastermind 46460 points

    Topi,

    The link to the ZIP file containing the spreadsheet is at the end of the Introduction in the Init guide at the link provided.  The ZIP file containing the latest REG_CALC worksheet is available at: http://www.ti.com/lit/zip/sprabx7.

    I will add you correction in my working copy.

    Tom