sysclkout stops after switching to PLL mode

Jens Biltoft

I want to use the SYSCLKOUT to verify the core frequency of my C6657 after I call platform_init to initialize the main PLL with default values.

What I see when I run my code is that the SYSCLOCKOUT gives a 16,67MHz signal for approx. 8ms and after that it gives a constant signal.

When I single step through

Platform_STATUS platform_init(platform_init_flags * p_flags,platform_init_config * p_config)

I can see that SYSCLOCKOUT is disabled until the function CorePllcHwSetup

executes this code

/* 3b. Clear PLLENSRC bit (enable PLLEN to control PLL controller mux) */
hPllcRegs->PLLCTL &= ~(1 << 5);

At that point the output starts toggling with 16,6MHz (=100MHz/6), and it keeps toggling the output until the end of this function where this code is executed

/* 14. In PLLCTL, write PLLEN = 1 (enable PLL contoller mux to switch to PLL mode) */
hPllcRegs->PLLCTL |= (1 << 0);

During all the time the SYSCLKOUTEN bit in DEVCFG register (0x0262014C) remains 1 so the output should be toggling right?

Can anyone tell me how the SYSCLOCKOUT can be disabled when the SYSCLKOUTEN bit in DEVCFG is set?

Best

Jens

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi Jens,

I'm not an expert in this, so I'm going to ask a colleague to comment on this.

Thank you for your patience.

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Hello Jens,

The SYSCLKOUT will be available at all time unless otherwise the SYSCLKOUTEN is disabled.

What is the PLL settings used in your code ?

Can you check the status of PLLDIV7.D7EN (Bit 15) when the SYSCLKOUT is disabled in PLL mode ?

Have you followed proper PLL initialization provided in PLL user guide ? I think the PLL controller is not properly entered into the PLL mode. Are you able to see other functions in your board after switching to PLL mode ?

Are you using TI provided example or your custom code ?

If possible please share your PLL initialization code ?

Regards,

Senthil

0 Jens Biltoft over 9 years ago in reply to Senthilkumar Srinivasan

Expert 1220 points

Hi Senthil

I am using the platform library from TI to initialize the PLL. I have just reinstalled pdk_C6657_1_1_2_6 to ensure that I had not made any changes to the lib.

void main()
{
	platform_init_flags InitFlag;
	platform_init_config InitConfig;

  init_emif();

  /* Initialize main Platform lib */
	memset(&InitConfig, 0, sizeof(platform_init_config));
	InitFlag.pll = 1;
	InitFlag.ddr = 0;
  InitFlag.phy = 0;
  InitFlag.ecc = 0;
	if (platform_init(&InitFlag, &InitConfig) != Platform_EOK)

from platform.c

Platform_STATUS platform_init(platform_init_flags  * p_flags,
        					  platform_init_config * p_config)
{
    CSL_Status              status;
    PllcHwSetup             pllc_hwSetup;
    PllcHwSetup             pllc_hwSetupRead;

#ifdef PLATFORM_PLL_REINIT
    int loop_count;
#endif

    /*************************************************************************
     * This routine may be called before BIOS or the application has loaded.
     * Do not try and write debug statements from here.
     ***********************************************************************/

    if ((p_flags == 0) || (p_config == 0)){
        platform_errno = PLATFORM_ERRNO_INVALID_ARGUMENT;
        return ( (Platform_STATUS) Platform_EFAIL);
    }

    /* Start TCSL so its free running */
    CSL_chipWriteTSCL(0);

#ifdef PLATFORM_PLL_REINIT
    for (loop_count = 0; loop_count < 10; loop_count++) {
        platform_errno = 0;
#endif

        /* PLLC module handle structure */
        if (p_flags->pll) {

            /* Set the Core PLL */
            /* Clear local data structures */
            memset(&pllc_hwSetup, 0, sizeof(PllcHwSetup));

            /* Setup PLLC hardware parameters */
            pllc_hwSetup.divEnable  = (CSL_BitMask32) (PLLC_DIVEN_PLLDIV2 |
                                                       PLLC_DIVEN_PLLDIV5 |
                                                       PLLC_DIVEN_PLLDIV8) ;

            /* Setup PLLC hardware parameters */        
            pllc_hwSetup.pllM       = 
                    (((p_config->pllm) ? p_config->pllm : PLATFORM_PLL1_PLLM_val) - 1);
            pllc_hwSetup.preDiv   = PLATFORM_PLL_PREDIV_val - 1;
            pllc_hwSetup.pllDiv2  = PLATFORM_PLLDIV2_val - 1;
            pllc_hwSetup.pllDiv5  = PLATFORM_PLLDIV5_val - 1;
            pllc_hwSetup.pllDiv8  = PLATFORM_PLLDIV8_val - 1;
            pllc_hwSetup.postDiv  = PLATFORM_PLL_POSTDIV_val -1;

            /* set Pll */
            status = CorePllcHwSetup (&pllc_hwSetup);
...

pllc_hwSetup struct PllcHwSetup {...} 0x0C094D70

divEnable unsigned int 1 0x0C094D70

pllM unsigned int 19 0x0C094D74

pllDiv2 unsigned int 2 0x0C094D78

pllDiv5 unsigned int 4 0x0C094D7C

pllDiv8 unsigned int 63 0x0C094D80

preDiv unsigned int 0 0x0C094D84

postDiv unsigned int 1 0x0C094D88

From evmc6657.c

CSL_Status CorePllcHwSetup (
        PllcHwSetup          *hwSetup
        )
{
    CSL_Status       status = CSL_SOK;
    volatile uint32_t i, loopCount;
    uint32_t temp;

    /* Unlock the Boot Config */
    CSL_BootCfgUnlockKicker();


    /* 1. Wait for Stabilization time (min 100 us)                             *
     * The below loop is good enough for the Gel file to get minimum of        *
     * 100 micro seconds, this should be appropriately modified for port       *
     * to a C function                                                         *
     * Minimum delay in GEL can be 1 milli seconds, so program to 1ms=1000us,  *
     * more than required, but should be Okay                                  */
    pll_delay(140056);

    /* 2. If PLL previously configured in RBL, avoid di/dt supply excursion by    *
     * matching PLL output to RefClk rate                                      *
     * if RBL configures the PLL, the BYPASS bit would be set to '0'           */
    temp = hPllcRegs->SECCTL &  0x00800000; /* Check the Bit 23 value */

    if (temp != 0) /* PLL BYPASS is enabled, we assume if not in Bypass ENSAT = 1 */
    {
        /* 2a. Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control *
         * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1.          *
         * The PLL initialization sequence in the boot ROM sets this bit to 0 and        *
         * could lead to non-optimal PLL operation. Software can set the bit to the      *
         * optimal value of 1 after boot                                                 *
         * Ref: http://www.ti.com/lit/er/sprz334b/sprz334b.pdf                           *
         * |31...7   |6     |5 4       |3...0      |                                     *
         * |Reserved |ENSAT |Reserved  |BWADJ[11:8]|                                     */

    	hBootCfg->CORE_PLL_CTL1 = hBootCfg->CORE_PLL_CTL1 | 0x00000040;

        /* 2b. Clear PLLEN bit */
    	hPllcRegs-> PLLCTL &= ~(1 << 0);
        
        /* 2c. Clear PLLENSRC bit */
    	hPllcRegs-> PLLCTL &= ~(1 << 5);

        /* 2d. Wait for 4 RefClks                                 *
         * Assuming slowest Ref clock of 25MHz, min: 160 ns delay */
        pll_delay(225);

        /* 2e. Bypass needed to perform PWRDN cycle for C6657	                     *
         * Needed on all devices when in NOBOOT, I2C or SPI boot modes               *
         * Ref: Figure 4-2 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf         *
         * PLL Secondary Control Register (SECCTL)  Layout                           *
         * |31...24  |23     |22...19       |18...0   |                              *
         * |Reserved |BYPASS |OUTPUT DIVIDE |Reserved |                              */

        hPllcRegs->SECCTL |= 0x00800000; /* Set the Bit 23 */

        /* 2f. Advisory 8: Multiple PLLs May Not Lock After Power-on Reset Issue     *
         * In order to ensure proper PLL startup, the PLL power_down pin needs to be *
         * toggled. This is accomplished by toggling the PLLPWRDN bit in the PLLCTL  *
         * register. This needs to be done before the main PLL initialization        *
         * sequence                                                                  *
         * Ref: Figure 4-1 of http://www.ti.com/lit/ug/sprugv2a/sprugv2a.pdf         *
         * PLL Control Register (PLLCTL)  Layout                                     *
         * |31...4   |3      |2        |1        |0        |                         *
         * |Reserved |PLLRST |Reserved |PLLPWRDN |Reserved |                         */

        hPllcRegs-> PLLCTL   |= 0x00000002; /*Power Down the PLL */

        /* 2g. Stay in a loop such that the bit is set for 5 µs (minimum) and       *
         * then clear the bit.                                                      */

        pll_delay(14005);

        /* 2h. Power up the PLL */  
        hPllcRegs-> PLLCTL   &= ~(0x00000002);

    }
    else
    {
        /* 3. Enable BYPASS in the PLL contoller */
        
        /* 3a. Clear PLLEN bit (bypass enabled in PLL controller mux) */
        hPllcRegs->PLLCTL &= ~(1 << 0);
        
        /* 3b. Clear PLLENSRC bit (enable PLLEN to control PLL controller mux) */
        hPllcRegs->PLLCTL &= ~(1 << 5);
        
        /* 3c. Wait for 4 RefClks (to make sure the PLL controller *
         * mux switches properly to bypass)                        *
         * Assuming slowest Ref clock of 25MHz, min: 160 ns delay  */
        pll_delay(225);
    }

    /* 4, 5, 6 and 7 are done here:                                              *
     * Program the necessary multipliers/dividers and BW adjustments             */
    prog_pll1_values(hwSetup);
    
    /* 8. Set PLL dividers if needed */

    /* part of 8, go stat bit needs to be zero here                             *
     * Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to      *  
     * indicate that the GO operation has completed                             *
     * wait for the GOSTAT, but don't trap if lock is never read                */
    for (i = 0; i < 100; i++) {
        pll_delay(300);
        if ( (hPllcRegs->PLLSTAT & 0x00000001) == 0 ) {
            break;
        }
    }
    if (i == 100) {
        return CSL_ESYS_FAIL;
    }

    /* part of 8, Set PLL dividers if needed */
    hPllcRegs->PLLDIV1_3[1] = (0x8000) | (hwSetup->pllDiv2);
    hPllcRegs->PLLDIV4_16[1] = (0x8000) | (hwSetup->pllDiv5);
    hPllcRegs->PLLDIV4_16[4] = (0x8000) | (hwSetup->pllDiv8);

    /* part of 8, Program ALNCTLn *
     * Set bit 1, 4 and 7         */
    hPllcRegs->ALNCTL |= ( (1 << 1) | (1 << 4) | (1 << 7));

    /* part of 8, Set GOSET bit in PLLCMD to initiate the GO operation to change the divide *
     * values and align the SYSCLKs as programmed                                */
    hPllcRegs->PLLCMD     |= 0x00000001;

    /* part of 8, Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to      *  
     * indicate that the GO operation has completed                                        *
     * wait for the GOSTAT, but don't trap if lock is never read                           */
    for (i = 0; i < 100; i++) {
        pll_delay(300);
        if ( (hPllcRegs->PLLSTAT & 0x00000001) == 0 ) {
            break;
        }
    }
    if (i == 100) {
        return CSL_ESYS_FAIL;
    }
    
    /* 9. Place PLL in Reset, In PLLCTL, write PLLRST = 1 (PLL is reset)         */
    hPllcRegs-> PLLCTL |= 0x00000008;
    
    /* 10. Wait for PLL Reset assertion Time (min: 7 us)                         */
    pll_delay (14006);

    /* 11. In PLLCTL, write PLLRST = 0 to bring PLL out of reset */
    hPllcRegs->PLLCTL &= ~(0x00000008);

    /* 12. PLL Lock Delay needs to be 500 RefClk periods * (PLLD + 1)           *
     * i.e., Wait for at least 500 * CLKIN cycles * (PLLD + 1) (PLL lock timer) *
     * Using 2000 25ns RefClk periods per DM                                    *
     * Wait for PLL to lock min 50 us                                           */
    pll_delay (140056 >> 1);
    
    /* 13. In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */
    hPllcRegs->SECCTL &= ~(0x00800000); /* Release Bypass */

    /* 14. In PLLCTL, write PLLEN = 1 (enable PLL contoller mux to switch to PLL mode) */
    hPllcRegs->PLLCTL |= (1 << 0);
    
    /* 15. The PLL and PLL Controller are now initialized in PLL mode - Completed. */

    return status;
}

After executing CorePllcHwSetup SYSCLKOUT is constant 0V, and The PLL registers have the following settings

(CSL_PllcRegs*)0x02310000 struct CSL_PllcRegs * 0x02310000 (Hex)

*((CSL_PllcRegs*)0x02310000) struct CSL_PllcRegs {...} (Hex) 0x02310000

RSVD0 unsigned char[228] 0x02310000 (Hex) 0x02310000

RSTYPE unsigned int 0x00000001 (Hex) 0x023100E4

RSTCTRL unsigned int 0x00010003 (Hex) 0x023100E8

RSTCFG unsigned int 0x00000000 (Hex) 0x023100EC

RSISO unsigned int 0x00000000 (Hex) 0x023100F0

RSVD1 unsigned char[12] 0x023100F4 (Hex) 0x023100F4

PLLCTL unsigned int 0x00000041 (Hex) 0x02310100

RSVD2 unsigned char[4] 0x02310104 (Hex) 0x02310104

SECCTL unsigned int 0x00090000 (Hex) 0x02310108

RSVD3 unsigned char[4] 0x0231010C (Hex) 0x0231010C

PLLM unsigned int 0x00000013 (Hex) 0x02310110

PREDIV unsigned int 0x00000000 (Hex) 0x02310114

PLLDIV1_3 unsigned int[3] 0x02310118 (Hex) 0x02310118

[0] unsigned int 0x00008000 (Hex) 0x02310118

[1] unsigned int 0x00008002 (Hex) 0x0231011C

[2] unsigned int 0x00008001 (Hex) 0x02310120

RSVD4 unsigned char[4] 0x02310124 (Hex) 0x02310124

POSTDIV unsigned int 0x00000000 (Hex) 0x02310128

RSVD5 unsigned char[12] 0x0231012C (Hex) 0x0231012C

PLLCMD unsigned int 0x00000001 (Hex) 0x02310138

PLLSTAT unsigned int 0x00000006 (Hex) 0x0231013C

ALNCTL unsigned int 0x00001FFF (Hex) 0x02310140

DCHANGE unsigned int 0x00000000 (Hex) 0x02310144

CKEN unsigned int 0x00000000 (Hex) 0x02310148

CKSTAT unsigned int 0x00000000 (Hex) 0x0231014C

SYSTAT unsigned int 0x00001FFF (Hex) 0x02310150

RSVD6 unsigned char[12] 0x02310154 (Hex) 0x02310154

PLLDIV4_16 unsigned int[13] 0x02310160 (Hex) 0x02310160

[0] unsigned int 0x00008002 (Hex) 0x02310160

[1] unsigned int 0x00008004 (Hex) 0x02310164

[2] unsigned int 0x0000803F (Hex) 0x02310168

[3] unsigned int 0x00008005 (Hex) 0x0231016C <= PLLDIV7.D7EN = 1 (bit15)

[4] unsigned int 0x0000803F (Hex) 0x02310170

[5] unsigned int 0x0000800B (Hex) 0x02310174

[6] unsigned int 0x00008002 (Hex) 0x02310178

[7] unsigned int 0x00008005 (Hex) 0x0231017C

[8] unsigned int 0x00008003 (Hex) 0x02310180

[9] unsigned int 0x00008007 (Hex) 0x02310184

[10] unsigned int 0x00000000 (Hex) 0x02310188

[11] unsigned int 0x00000000 (Hex) 0x0231018C

[12] unsigned int 0x00000000 (Hex) 0x02310190

The DEVCFG register at 0x0262014C have the value 0x00000001

After initializing PLL, my application runs normally, and I am sure the core frequency is in fact 1GHz, because I have initialized some timers that toggles output pins at the expected rate. It seems that the only thing that does not work is the SYSCLKOUT.

Best

Jens

0 Senthilkumar Srinivasan over 9 years ago in reply to Jens Biltoft

TI__Mastermind 43660 points

Hello Jens,

Are you testing this code on EVM or custom board ?

Is there any circuit connected to SYSCLKOUT pin ?

Could you please run C6657 gel file in your board using CCS and try you can reproduce this issue ?

Meanwhile i will also check the SYSCLKOUT functionality in the EVM.

Regards,

Senthil

0 Jens Biltoft over 9 years ago in reply to Senthilkumar Srinivasan

Expert 1220 points

I have tried running the code both on EVM and on my own board, with the same result

I have now tried creating a helloworld_evmc6657 project where I have added som testing of DDR3 ram.

This project does excactly the same regardless if I run it on EVM or my own board.

If I do not run PLL init using the GEL script I get a SYSCLKOUT frequency of 16.67MHz, but as soon as I execute the PLL initialization usihng the GEL script the SYSCLK stops toggling.

I have attached the project so you can test it

Thanks

Jens

0358.helloworld_evmc6657l.zip.txt

0 Senthilkumar Srinivasan over 9 years ago in reply to Jens Biltoft

TI__Mastermind 43660 points

Hello Jens,

What is the bandwidth of the scope you are using for SYSCLKOUT measurement ?

Could you please share the waveform of SYSCLKOUT before and after PLL intialization using gel script.

Regards,

Senthil

0 Jens Biltoft over 9 years ago in reply to Senthilkumar Srinivasan

Expert 1220 points

You may be on to something here. I have been using a 60MHz scope, but now I have switched to a 400MHz.

When I now measure on the EVM, I se a 166MHz signal with an amplitude of 500mV and a DC ofset of about 1V

On my own board I still do not see anything, but it may be related to the circuit conected to the SYSCLKOUT pin. I will check with the HW department.

Thanks

Jens

0 Senthilkumar Srinivasan over 9 years ago in reply to Jens Biltoft

TI__Mastermind 43660 points

Hello Jens,

Thanks for the update.

The 166MHz signal at SYSCLKOUT is the expected one after PLL initialization (1 GHz / 7 = 166 MHz). I also verified this in the EVM.

Please check the circuit connected to the SYSCLKOUT pin for any issues with the design. If possible isolate the circuit and check the output clock.

Regards,

Senthil

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sysclkout stops after switching to PLL mode