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K2EVM_HK L2 Cache size (Program and Data memory configuration)

Narendra Kumar Chepuri
Prodigy 195 points

Hi Rajasekaran,

              We are working on K2EVM_HK(TCI6638K2H) is there any datasheet which explains about memory distribution of SRAM and can we get the information regarding L2 Cache size and how it is disributed? It will be helpful if you provide the datasheet and explain about the memory distribution. 

Thank & Regards,

Narendra Kumar Chepuri.

  • 0
    TI__Guru* 81335 points

    HI Narendra,

    Please refer corepac user guide for DSP & ARM memory distribution.

    C6000 DSP: http://www.ti.com/lit/sprugw0

    ARM A15: http://www.ti.com/lit/spruhj4

    Also refer ARM cortex a15 technical reference manual.

    Thank you.

  • 0 in reply to Raja
    Prodigy 195 points

    Hi Rajasekaran,

                Links you shared doesn't have how L2 Cache is configured they are telling it has 4 Mb of L2 cache is shared between 4 Arm Cores, but they have not mention out of 4 Mb how much is allotted as a Data memory and how much is allotted as a Program memory. They are also mentioning that it has Configurable Cache How can we configure cache? Can you provide the details like if per core 1 Mb of cache is there out of which what are the sizes of program and data memories?

     Thanks & Regards,                                                                                                                                                      

    Narendra Kumar Chepuri.

  • 0 in reply to Narendra Kumar Chepuri
    TI__Guru* 81335 points

    Hi,

    Please refer below post and help us to close this thread.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/386543/1365478.aspx#1365478

    Thank you.