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Minimum boot configuration for Ethernet boot

Sebastian Suesens
Intellectual 645 points
Other Parts Discussed in Thread: 66AK2E05

Hello,

I have a 66AK2E05 CPU. I want to boot the processor via ethernet with minimum boot pin select, but it doesn't work.

The PA clk source is NETCPCLK (156,25MHz) select via NETCPCLKSEL = 1. I think the Ref Clock coming from the SGMII clock (156,25MHz). The core clock is 156,25MHz. 

When the system is configured with non minimum boot pin select and the other pins have the default values for ethernet minimum boot pin select it works. I test the minimum boot pin select for uart and spi and it works.

Can anyone help me?

  • 0
    TI__Guru* 81335 points

    Sebastian,

    Could you please post the selected min boot pin configuration for Ethernet? are you working on custom board with 66AK2E05 ?

    The above post confused me, could you please elaborate the issue?

    Thank you.

  • 0 in reply to Raja
    Intellectual 645 points

    Hello,

    yes I work on a custom board with 66AK2E05.The table below shows my configuration. The default value mean that the CPU doesn't read the pin value, it takes the showing value as default.

    16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    Pa Clk Ref Clock Ref Clock Ext Con Ext Con Lane Setup Lane Setup Lane Setup Boot Master Sys Pll Cfg Sys Pll Cfg Sys Pll Cfg Min 1 0 1 Lendian
    default 1 default 0 default 1 default 0 default 1 default 0 default 0 default 0 0 default 1 default 0 default 0 1 1 0 1 1

    PA Clk: PA clocked at the same reference as the SerDes reference. -> What does it mean?

    Ref Clock: SRIO Reference clock frequency. -> What does it mean?

    The issue:

    When I want to boot from ethernet with minimum boot pin select, I can't boot from ethernet. When I use non minimum boot pin select (see table below) the CPU boots from ethernet. In non minimum boot pin select I only change bit 4 from 1 to 0. The other values should be the same as for minimum boot pin select.

    16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    Pa Clk Ref Clock Ref Clock Ext Con Ext Con Lane Setup Lane Setup Lane Setup Boot Master Sys Pll Cfg Sys Pll Cfg Sys Pll Cfg Min 1 0 1 Lendian
    1  0  1  0  1 0  0  0 0  1  0  0 0 1 0 1 1
  • 0 in reply to Sebastian Suesens
    TI__Mastermind 43660 points

    Hello Sebastian,

    PA Clk: PA clocked at the same reference as the SerDes reference. -> What does it mean?

    I will check on this and come back.

    Ref Clock: SRIO Reference clock frequency. -> What does it mean?

    The value in Ref Clock field selects the SGMII reference clock frequency as 125MHz or 156.25MHz.

    How do you change the value of minimum boot configuration select bit ? have you hardwired the BOOTMODE pin 3 to change the minimum boot value ? If so, what about other pins of BOOTMODE ?

    Regards,

    Senthil

  • 0 in reply to Sebastian Suesens
    TI__Mastermind 43660 points

    Hello Sebastian,

    PA Clk: PA clocked at the same reference as the SerDes reference. -> What does it mean?

    PASS PLL configuration assumes input rate same as SRIOSGMIICLK(P/N). The Ethernet boot mode require that the PACLK frequency match the SGMIICLK frequency.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Intellectual 645 points

    Hello Senthil,

    now I test the minimum boot pin select wit the K2E_EVM Board. When I want to boot with bootmode value 0x0 0x1508B the K2E starts with ethernet boot. When I change the bootmode value to 0x0 0x1509B it doesn't start.

    Do you have any idea why?

  • 0 in reply to Sebastian Suesens
    Intellectual 645 points

    Hello Senthil,

    back to my custom board.

    The CORECLK from the custom board is 156,25MHz.

    The SGMIIClock from the custom board is 156,25MHz.

    The NETCPCLKSEL is zero, so that the PACLK use the CORECLK.

    Is the configuration for the clocks right?

  • 0 in reply to Sebastian Suesens
    TI__Mastermind 43660 points

    Hello Sebastian,

    The CORECLK from the custom board is 156,25MHz.

    The SGMIIClock from the custom board is 156,25MHz.

    The NETCPCLKSEL is zero, so that the PACLK use the CORECLK.

    Is the configuration for the clocks right?

    Yes, this clock configuration is correct.

    Further on minimum boot issue, we will check on this and update you.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    TI__Guru** 114410 points

    Sebastian,

    The ethernet boot on K2E is impacted by the issue reported in advisory 25 of the device errata.  Please check the issue with K2E Ethernet boot described here in the errata here :

    http://www.ti.com/lit/er/sprz417/sprz417.pdf

    You will need to implement the work around code to boot over ethernet. We have a sample implementation of the work around on the EVM that we can share with you if you like.

    Can you please clarify what you mean by ethernet boot works when you set the pins to 0x1508B? Do you see bootp from the device?

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 645 points

    Hello Rahul,

    to your question.

    When I configured the BMC with the value 0x1508B, I see bootp from the device.

    When I configured the BMC with the value 0x1509B, I see no bootp from the device.



    Regards,

    Sebastian

  • 0 in reply to Sebastian Suesens
    Intellectual 645 points

    Hello Rahul,


    my custom board boots with the configuration value 0x1508B.

    On some boards I have the network issue which you describe. Can you explain me the workaround.

    When is the issue fixed?

    Best regards,

    Sebastian