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SRIO Direct IO througput between two SoC

Hi

I am using  SRIO_LpbkDioIsrK2KC66BiosExampleProject from pdk. We developed a card that include two SoC(Keystone II).

I tested exp project with loopback mode. But now, I am trying to test througput between two SoC. In our card, first and second ports of SRIO's are connected to secondary SoC. The other ports connect different cores exceed from card.

So what should I change  for testing DirectIO operation between two card? I couldn't see any define  for change loopback mode to external connection?

Could you give some information about it?

Thanks

  • Hi,

    Regarding non-loopback mode, you need to change the below code:

    /* Configure SRIO to operate in loopback mode. */
    //    CSL_SRIO_SetLoopbackMode(hSrio,0);
    //    CSL_SRIO_SetLoopbackMode(hSrio,1);
    //    CSL_SRIO_SetLoopbackMode(hSrio,2);
    //    CSL_SRIO_SetLoopbackMode(hSrio,3);
    /* Configure SRIO to operate in normal mode. */
      CSL_SRIO_SetNormalMode(hSrio,0);    
      CSL_SRIO_SetNormalMode(hSrio,1);    
      CSL_SRIO_SetNormalMode(hSrio,2);    
      CSL_SRIO_SetNormalMode(hSrio,3);

    Also check the Receive/Transmit SRIO SERDES Configuration on your code.

    /* Configure the SRIO SERDES Receive Configuration. */
    /* Non-loopback */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x00440495);
     
    /* Configure the SRIO SERDES Transmit Configuration. */
    /* Non-loopback */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00180795);


    There is also another SRIO example in the MCSDK that can run in loopback or board to board. I have tested this example in loopback and board to board modes successfully. Better to try this SRIO example for your testing

    MCSDK Path: C:\ti\pdk_keystone2_3_01_01_04\packages\exampleProjects\SRIO_TputBenchmarkingK2KC66TestProject

    Refer section "5.3 Two EVMs connected using breakout cards" and "9.4 Setting up B-E-B connection mode (board to board, external interface)" on SRIO Benchmarking Example Code user guide.

    Doc Path: "\ti\pdk_keystone2_3_01_00_03\packages\ti\drv\srio\test\tput_benchmarking\docs"

    Thanks,

  • Thanks for your reply,

    I want to ask another question; Should I load same code to receiver side or only setting SerDes for SRIO is enough ? Are there any config on receiver side ?

  • ** I am asking regarding SRIO_LpbkDioIsrK2KC66BiosExampleProject
  • On the other hand, I tried SRIO_TputBenchmarkingK2KC66TestProject for board to board ; My workflow like as below from .doc;

    Change the “IS_BOARD_TO_BOARD” define from “FALSE to “TRUE”, this will automatically set loopback mode to off and have the output show that the test was run board to board.
    Recompile the project.
    Save the compiled consumer .out file to a separate directory.
    Modify the benchmarking.h file in the following way for the producer .out file:
    Change the “IS_BOARD_TO_BOARD” define from “FALSE to “TRUE”, this will automatically set loopback mode to off and have the output show that the test was run board to board.
    Change the “CORE_TO_INITIALIZE_SRIO” define from “CONSUMER_CORE” to “PRODUCER_CORE”. This will allow the srio initialization routine to be executed for the producer EVM.
    Recompile the project.
    Load and run the consumer .out file from the saved directory on core 0 of the first EVM. This will be the receive side for the SRIO transfer. The consumer .out file must be loaded and run before the producer .out file is run.
    Load and run the producer .out file on core 1 on the second EVM. This will be the transmit side for the SRIO transfer. This should start the transfer

    but I take error like this;

    Debug: SRIO port 0 is NOT operational.
    Debug: SRIO port 1 is NOT operational.
    Debug: SRIO port 2 is NOT operational.
    Debug: SRIO port 3 is NOT operational.
    Debug: Lanes status shows lanes formed as four 1x ports
    Debug: AppConfig Tx Queue: 0x2a0 Flow Id: 0
    Debug: SRIO Driver Instance 0x@00862fc0 has been created
    Debug: Running test in polled mode.
    Debug: SRIO Driver handle 0x862fc0.


    Error: Binding the DIO Management Socket failed.

    What is the meaning of this error? I change possible values for SRIO lane mode but I am taking this error for each lane mode ?

    Thanks
  • Hi,

    I think the SRIO lanes are not properly connected to other device SRIO lanes.

    Have you using BOC for connecting two EVM?

    The details can be found at: http://processors.wiki.ti.com/index.php/CI_Dual_EVM_Break_Out_Card

    Regarding SRIO_LpbkDioIsrK2KC66BiosExampleProject, You can load the same .out flie for both Tx/Rx DSP devices core0.

    Thanks,

  • I guess I undertand the problem. We use two SerDes lane to secondary SoC, other third and fourth SerDes lane are connected different chip. I tried to change lane mode but all enums are set for 4 lane but I need 2 or 1 lane to map ports.

    How can I change number of used lane ?
  • I could sent data with SRIO but I needed some changes. If I set SRIO_DIO_LSU_ISR_NUM_SOCKETS value to 3, in Srio_validateDIOBindingId(ptr_dioInfo->srcIDMap, ptr_dioInfo->idSize) function I take an error at slave side but in master side there is no problem. So I changed SRIO_DIO_LSU_ISR_NUM_SOCKETS to 1, then I could send data between SoC.

    As I said before, . We use two SerDes lane to secondary SoC, other third and fourth SerDes lane are connected different chip
    Are there any relation between this case and SRIO_DIO_LSU_ISR_NUM_SOCKETS value?

    Thanks