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C6670 clocking

Other Parts Discussed in Thread: TMS320C6670

In our design we use two TI TMSe320C6670 DSPs connected to an FPGA. We intend to use the SRIO interfaces as four 1-lane plus the Hyperlink between each DSP and FPGA.

Our clock is 153.6 MHz which we would like to uniquely drive to each of the TI DSP clock inputs:

SYSCLKP/N

DDRCLKP/N

MCMCLKP/N

SRIOSGMIICLKP/N

We are not using PASSCLKP/N, PCIECLKP/N, or RP1CLKP/N and they are tied off per TI recommendations. 

From the documentation it is inferred several places that the ONLY valid clock frequencies for SRIOSGMIICLKP/N and MCMCLKP/N are 156.25, 250, or 312.5 MHz.

Also, it appears from TI document SPRS689D in table 2-12 that ONLY Hyperlink reference clock configuration of 156.25,250, and 312.5 MHz are selectable.

Can someone confirm this to be the case that we MUST use either 156.25,250, or 312.5 MHz for both SRIOSGMIICLKP/N and MCMCLKP/N clock inputs to the TI TMS320C6670 DSP?