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C6678 SRIO port speed

JPH-FR
Prodigy 231 points

Hi,

 

We have a custom board in which a C6678 is connected to 4 SRIO endpoints through 4 1X ports.

Two of these endpoints work at 1.25 GHz and the two others work at 5 GHz.

I’m not able to initialize 2 ports at 1.25 Ghz (ports 0 and 1) and 2 ports at 5 GHz (ports 2 and 3) at the same time.

In all the following manipulations, the value of SRIO_SERDES_GFPLL is 0x251

 

Case 1: Result as expected

SRIO_SERDES_GFRX0 =0x004404B5       SRIO_SERDES_GFTX0 = 0x00180035 ==> Port 0 Ok at 1.25 GHz

SRIO_SERDES_GFRX1 =0x004404B5       SRIO_SERDES_GFTX1 = 0x00180035 ==> Port 1 Ok at 1.25 GHz

SRIO_SERDES_GFRX2 =0x004404B5       SRIO_SERDES_GFTX2 = 0x00180035 ==> Port 2 KO at 1.25 GHz (normal because connected to a 5GHz endpoint)

SRIO_SERDES_GFRX3 =0x004404B5       SRIO_SERDES_GFTX3 = 0x00180035 ==> Port 3 KO at 1.25 GHz (normal because connected to a 5GHz endpoint)

 

Case 2: Result as expected

SRIO_SERDES_GFRX0 =0x00440495       SRIO_SERDES_GFTX0 = 0x00180015 ==> Port 0 KO at 5 GHz (normal because connected to a 1.25 GHz endpoint)

SRIO_SERDES_GFRX1 =0x00440495       SRIO_SERDES_GFTX1 = 0x00180015 ==> Port 1 KO at 5 GHz (normal because connected to a 1.25 GHz endpoint)

SRIO_SERDES_GFRX2 =0x00440495       SRIO_SERDES_GFTX2 = 0x00180015 ==> Port 2  OK at 5GHz

SRIO_SERDES_GFRX3 =0x00440495       SRIO_SERDES_GFTX3 = 0x00180015 ==> Port 3 OK at 5GHz

 

 

Case 3: Result not as expected: Why port 2 and port 3 are not OK ?

SRIO_SERDES_GFRX0 =0x004404B5       SRIO_SERDES_GFTX0 = 0x00180035 ==> Port 0 Ok at 1.25 GHz

SRIO_SERDES_GFRX1 =0x004404B5       SRIO_SERDES_GFTX1 = 0x00180035 ==> Port 1 Ok at 1.25 GHz

SRIO_SERDES_GFRX2 =0x00440495       SRIO_SERDES_GFTX2 = 0x00180015 ==> Port 2 KO at 5GHz (although connected to a 5 GHz endpoint)

SRIO_SERDES_GFRX3 =0x00440495       SRIO_SERDES_GFTX3 = 0x00180015 ==> Port 3 KO at 5GHz (although connected to a 5 GHz endpoint)

 

Why in case 3 are port 2 and 3 not OK , while they are OK in case 2 with the same register values?

Thanks,

JP

  • 0
    TI__Mastermind 28085 points

    Hi,

    For my understanding your SRIO serdes configuration steps are correct.

    I have modified the below changes in SRIO throughput example code and tested the SRIO transfer in loopback mode. It is working fine.

    	/* Configure the SRIO SERDES Receive Configuration. */
	CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);
	CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x01C40495);
	CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x01C404B5);
	CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x01C404B5);

	/* Configure the SRIO SERDES Transmit Configuration. */
	CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);
	CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00780795);
	CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x007807B5);
	CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x007807B5);

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 231 points

    Hi,

    Thanks for your quick reply.

    I tried the configuration you suggest on my board and I get the following status: Ports 0 and 1 OK, Port 2 and 3 KO.


    Here is the corresponding screen copy for the SERDES and port registers:

     With the loopback on the SERDES, the port status doesn't depend on the  endpoints connected to them.

    Are they some registers I missed that could explain this result ?

    Thanks for your help,

    JP

  • 0 in reply to JPH-FR
    Prodigy 231 points
    Hi Ganapath,

    I implemented the throughput example on my custom board and I had the same results as you. With these modifications, all 4 ports are OK:

    /* Configure SRIO to operate in Loopback mode. */
    CSL_SRIO_SetLoopbackMode (hSrio,0);
    CSL_SRIO_SetLoopbackMode (hSrio,1);
    CSL_SRIO_SetLoopbackMode (hSrio,2);
    CSL_SRIO_SetLoopbackMode (hSrio,3);


    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x01C404B5);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x01C404B5);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x007807B5);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x007807B5);

    In order to obtain 2 ports at 1.25 and 2 ports at 5 GHz, I made the following modifications from the code that was OK with the loopback:

    CSL_SRIO_SetNormalMode (hSrio,0);
    CSL_SRIO_SetNormalMode (hSrio,1);
    CSL_SRIO_SetNormalMode (hSrio,2);
    CSL_SRIO_SetNormalMode (hSrio,3);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x004404B5);
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x004404B5);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x01C40495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180035);
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00180035);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00180015);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00180015);

    With only these modification, I fall on the same problem as before: ports 1 and 2 are OK, ports 3 and 4 are KO.

    Is there something else to do to switch from a loopback situaiton OK to a normal situation OK?

    Thanks

    JP





    4 ports a