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Link training issues PCIE

Jeff Allred
Prodigy 20 points

I've seen this discussed quite a bit, but none of the posts helped resolve my problem.

I have a custom board with a C6655 connected to an Etron EJ198 over PCIe. Link training fails in state Polling.Compliance. I can see on a scope the receiver detect pulses coming from the DSP and if I put the Etron in reset then the receive detect stops on a failure.

I have 100nF caps in all the PCIe lanes with lengths matched and impedance controlled.

There seems to be a common thread of a clocking issue causing this problem. I'm using an Si52142 to generate the clock for the DSP and for the Etron. On a different prototype situation I used the same SI labs part to drive a clock to the Etron and to the 6657 EVM with success. The SiLabs part says that no termination resistors are required, so I have none. The outputs of the SiLabs part go through caps to the DSP for AC coupling. The other output goes directly to the Etron, just as it did on my previous prototype.

Could it be that there needs to be 50 ohm termination resistors to ground before the AC cap on the clock lines to the DSP? If so, could this lack of termination result in a link failure? When I try to link, I monitor the PLL lock bit and it is always set indicating that the PLL is locked.

Thanks

Jeff Allred

  • 0
    TI__Mastermind 43660 points

    Hello Jeff,

    Welcome to TI E2E forum!

    All differential clock inputs are implemented with Texas Instruments low jitter clock buffers (LJCBs). These input buffers include a 100 ohm parallel termination (P to N) and common-mode biasing. So external termination resistors are not needed.

    As you stated above, did you find any linking issue in your previous prototype with same clocking scheme ?

    What is the PCIe reference clock frequency ? Have you properly configured the PCIe SERDES registers ?

    Also, the improper power sequence might cause this issue. Please check the below wiki link.

    http://processors.wiki.ti.com/index.php/PCI_Express_%28PCIe%29_Resource_Wiki_for_Keystone_Devices

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 20 points

    Hello Senthil,

    Thanks for your reply. You say that the LJCBs don't need any termination resistors yet your EVM using them for HCSL based inputs. Also I read this exchange about HCSL into LJCB terminations:  http://e2e.ti.com/support/clocks/f/48/p/240818/848692

    I had no issues with my linking with my previous prototype.

    My PCIe reference clock frequency is 100 MHz. With the previous prototype, all of the default configuration registers were correct and I only had to start link training. 

    The power sequence is different between prototype and my current board. In the prototype it was the EVM and it used the standard startup sequence. I have attempted to do the equivalent startup, but it could possibly be a problem area. Is it mandatory that the PCIe reference clock is stable before the DSP is powered or brought out of reset?

    Thanks!

    Jeff

  • 0 in reply to Jeff Allred
    TI__Mastermind 43660 points

    Hello Jeff,

    In our EVM, we used a 2:1 clock multiplexer and the output termination is provided as per multiplexer guidelines. If you are not using any intermediate device in clock path, termination is not required for HCSL as well. There is a statement in keystone I hardware design guideline document, the LJCB will support a PCI express-compliant HCSL clock input and this clock is terminated in the same manner as an LVDS clock driver.

    The termination that you referred in the other thread is for DC coupled line. Because the LJCB includes common mode biasing, the clock source must be AC coupled.

    Is it mandatory that the PCIe reference clock is stable before the DSP is powered or brought out of reset?

    Please refer the below table extracted from HDRG.

    Regards,

    Senthil