Hi,
I'm afraid that I'm asking many things about uPP.
Question:
How much latency would be expected to invoke built-in DMA when receiving/transferring data via uPP ?
Background:
One of my (another) customer is now considering to use C6655 uPP in order to connect FPGA.
Their application requires very small latency in each data packet. And the packet size is very small, say 256 bytes per a packet.
A packet has to be transferred to/from FPGA. So uPP would be configured to share data lines between Rx/Tx, i.e., 8 data lines for Rx and 8 data lines for Tx.
Now let's consider about their Rx use case. A 256 bytes packet would be transferred to C6655's L2 memory.
I break the time taken by this use case into 2 phases :
phase 1 -- Time taken by getting data from FPGA to uPP's internal FIFO.
phase 2 -- Time taken by transferring the data from internal FIFO to C6655 L2 memory area.
Their system requirement is getting a packet in 6 usec, i.e., The total time taken by phase 1 and 2 has to be in 6 usec.
At the phase 1, clocking uPP with faster clock can reduce the time taken by transfer. If we assume to use 64 Mhz, the time taken by phase 1 would be 4 usec.
So the time taken by phase 2 has to be in 2 usec. I want to know the feasibility (2 usec at phase 2 is feasible or not). I know the behavior of their application code can slightly affect this value. For example, the transfer from uPP FIFO to L2 memory can be blocked if other master ports (CPU/EDMA/etc..) access to the L2 at the same timing, but I believe this would be in insignificant. The significant is the time to invoke built-in DMA itself. I could not find the answer via any documentations (uPP UG/ C6655 data sheet), so I'm asking the question here.
Again, uPP latency is very important in their system. I hope we could get the answer from you soon...
Best Regards,
Kawada