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C6678 Shared memory

Other Parts Discussed in Thread: TMS320C6678

Hello all,

I have a C6678 that interfaces with SPARTAN6 FPGA using PCIe. I am using Core 0 EDMA3 to read a block of data from the FPGA using the PCIe interface into core 0 LL2SRAM. I need all the cores to process the same data.

1- What is the BEST way to share the same data among all the cores?.

2- if I use MSMCSRAM, Can ALL COREs read the SAME memory location at the SAME time?

3- if to use MSMCSRAM, do I use core 0 EDMA3 to move data from FPGA to MSMCSRAM and EDMA3 (?) to move data from MSMCSRAM to LL2SRAM?

4- if I have each core read the data from MSMCSRAM into LL2SRAM without EDMA3, is reading MSMCSRAM is same speed as reading LL2SRAM?

Regards,

Murad

  • Hi Murad,

    Ans1: You can use the MSMCRAM memory for share the same data to all the cores.

    Ans2: For my understanding, all the core are not able to read the shared memory data at the same time. I will check with team and confirm the same.

    Thanks,
  • 1.) Depending on the activity levels of different cores there may be better ways to handle it, but in general MSMC is going to be the best place to keep data that is shared between cores.

    2.) MSMC is broken into 8 banks and each bank has 4 subbanks. So that these can be simultaneously accessed by different cores. That said, a particular address would not be able to be accessed by multiple cores on the same cycle.

    3.) I'd suggest moving data from FPGA to MSMC via whatever peripheral interface you normally use (may be using EDMA on top of it. Note that EDMA is a shared resource among the cores and not dedicated to a core, but I'd recommend having one core handle all the FPGA traffice.) I'd have L1D and L2 setup as cache, and let it be cached in as the various cores access it. Note that when the core modifies the data, it will need to perform a Writeback Invalidate to push the data back out of the L1D/L2 Cache to the MSMC RAM, else it will have stale data at that point.

    4.) The first time caching it into L2 will have the speed of a MSMC read, after that (while in cache) it will be either L1D speed (if resident in L1D) or at worst an L2 access (assuming it's cached into L2 space at the time of the access.)

    I'd highly recommend reviewing the C66x Cache User Guide and MSMC User Guide which is available in the technical documentation section of the TMS320C6678 <-- Product Page.

    Best Regards,
    Chad
  • Thanks guys for your inputs.
    Chad: I start reading the documents you suggested but I have a question: So core 0 reads a block of data (3072 int) from FPDA using PCIe/EDMA3 (working fine). to share it, does core 0 reads the data in core 0 memory and then copy it 7 times to different banks of MSMC (I guess we can use EDMA3 to do so)? Or do I let each core uses EDMA3 to read the data in LL2 (but all cores get interrupted to read data at same time)...Or I have core 0 call EDMA3 7 times to write data into each core's LL2...could you please describe the process a little more.

    PS: data movement is in one direction: From FPGA to cores

    Regards,

    Murad

  • btw: MSMC user guide (SPRUGW7A) talk a lot about memory protection and it didn't help much understanding the MSMC setup!
  • Can anyone help here please...I like to hear your inputs before I start a try and error techniques...

    Regards,

    Murad
  • Should I give up on this post!!!
  • I configure the shared memory and IPC, used MessageQ to pass the address of the buffer in MSM used in core 0 to store the FPGA data. Core 1 successfully read the data BUT the process is too slow...I had to slow my system 10 times in order to work (Not possible in our real application)...how can I speed the sharing of FPGA data with the other cores?...I'll give more info once I see anyone is willing to help!
  • What happened to TI customer service!!!...I used to get replies within a day or two...now I have posts waiting for reply for more than a month...Am I missing anything!!!
  • Excuse me, do I understand correctly, that I can not simultaneously write to L2 cache any cores via EDMA3
    and read to L2 the same cores via core pack with some offsets? And I should constantly used invalidate cache, after
    any action with cache?
    Best regards,
    Oleg