Hello all,
I have a C6678 that interfaces with SPARTAN6 FPGA using PCIe. I am using Core 0 EDMA3 to read a block of data from the FPGA using the PCIe interface into core 0 LL2SRAM. I need all the cores to process the same data.
1- What is the BEST way to share the same data among all the cores?.
2- if I use MSMCSRAM, Can ALL COREs read the SAME memory location at the SAME time?
3- if to use MSMCSRAM, do I use core 0 EDMA3 to move data from FPGA to MSMCSRAM and EDMA3 (?) to move data from MSMCSRAM to LL2SRAM?
4- if I have each core read the data from MSMCSRAM into LL2SRAM without EDMA3, is reading MSMCSRAM is same speed as reading LL2SRAM?
Regards,
Murad