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xmc_setup meaning

Alex S
Intellectual 545 points
Other Parts Discussed in Thread: TMS320C6678

Hi there.
Could someone explain what are for xmc_setup 4KB remapping procedure in evmc6678l.gel:

    /* mapping for ddr emif registers XMPAX*2 */
    XMPAX2_L = 0x100000FF;     /* replacement addr + perm*/
    XMPAX2_H =  0x2100000B;    /* base addr + seg size (64KB)*/  //"1B"-->"B" by xj

if in compliance with TMS320C6678 datasheet Table 2-2. Memory Map Summary 512 bytes of DDR3 EMIF configuration already mapped by default at 0x21000000 address?


And what does mean "seg size (64KB)*/  //"1B"-->"B" by xj" comment provided that

Thanks in advance.

  • 0
    TI__Guru* 81335 points
    Hi Alex,
    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    Please refer below thread for answer.
    e2e.ti.com/.../151934
  • 0 in reply to Raja
    Intellectual 545 points

    Thanks, but i'm still haven't clear and short explanation.

    If we need to do initial mapping for DDR3 EMIF configuration, why for DDR3 EMIF data it is not necessary?

    As written in datasheet that "memory map shows only the default MPAX configuration of DDR3 memory space". So why we need to do xmc_setup if it map the same addresses that should be already mapped by default according to Table 2-2?

  • 0 in reply to Alex S
    TI__Expert 6815 points

    Alex,

    I have addressed this question in a previous thread : http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/151934

    Please take a look and let us know if you have questions.

  • 0 in reply to Aditya
    Intellectual 545 points

    Aditya,

    i have read related threads already and there are no answers.

    If you get a quick precise question from a user, it is not normal to send him to read some links which again refer to some documentation.

    Your documentation is not good and clear enough as well as your answers.

    May be you will start to do one or other well??

  • 0 in reply to Alex S
    Intellectual 545 points

    Aaaand bump!

    ( ≖.≖)

  • 0 in reply to Alex S
    TI__Guru* 81335 points

    Hi Alex,

    The Table 2-2 shows the memory of C6678 device however the default reset status of MPAX configurations is documented in CorePac user guide(SPRUGW0C - Section Figure 7-10 Memory Map Reset Status).

    XMPAX0, XMPAX1 that is segment 0 and 1 will be used by default for memory protection and address extension.

    The below comment is applicable only to DDR3 EMIF data (2)

    (2) The memory map shows only the default MPAX configuration of DDR3 memory space. For the extended DDR3 memory space access (up to 8GB), see the MPAX configuration details in C66x CorePac User Guide and Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

    I hope this answers your question. Thank you.