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Question about OpenMP platforms

Oleg Borovikov
Expert 1280 points
Other Parts Discussed in Thread: TMS320C6678, SYSBIOS

Hi All,

I have question about platform for OpenMP to TMS320C6678
Into TI documentations about OpenMP by talks "Be aware that breaking these rules might result in an application that builds
fine but might (arbitrarily) malfunction at runtime" - ti/omp_1_01_03_02/docs/User Guide.pdf and
"If ‘dataMemory’ is set to a memory segment that lies in the physical address
range for MSMC RAM (0x0C000000), then L1D must be set to ‘0K’ to make this
address range non-cacheable".
Into file ti/omp_1_01_03_02/packages/ti/omp/examles/platforms/evm6678/Platform.xdc there is next:
/*!
* File generated by platform wizard. DO NOT MODIFY
*
*/
. . . .
["MSMCSRAM_NOCACHE", {name: "MSMCSRAM_NOCACHE", base: 0xA0100000, len: 0x00300000}],
],
l1DMode:"32k",
l1PMode:"32k",
l2Mode:"0k",

});


I trued run OMP exapmle with ti.omp.examples.platforms.evm6678 and receive


with ti.omp.examples.platforms.evm6678_ddr all examples run successfully

My question - this is contradiction into documentation or I understand something wrong?

Best Regards,

    Oleg

  • 0
    TI__Genius 10415 points

    Oleg,

    OpenMP requires that the 'dataMemory' be placed into a shared memory that is non-cacheable. The physical memory range for MSMC (0x0C000000-0x0C3FFFFF) is by default always cacheable. The MAR registers for the MSMC memory range are READ ONLY which means that the cacheability cannot be changed.

    Knowing this we have two options:

    1. Set the L1 and L2 caches to 0k and access the MSMC through its physical address range (0x0C000000 - 0x0C3FFFFF)
      1. This is the method that you are referring to from the user guide
      2. Since there are no caches then none of the memory accesses to the MSMC, or the DDR for that matter, will be cached
    2. Create a virtual address range that is non-cacheable that points to a portion of the MSMC's physical memory range.
      1. This is the method that the provided examples use
      2. In the platform.xdc file that you copied from above you can see that a virtual address range is being used to access part of the MSMC memory. 
      3. In this case 0xA0100000 - 0xA03FFFFF is an alias for the physical MSMC memory range 0x0C100000 - 0x0C3FFFFF
      4. The MAR registers for the 0xA0100000 - 0xA03FFFFF address range are configured to be non-cacheable so any MSMC memory access through this memory range will not be cached regardless of the size of the L1 or L2 caches

    Thanks,

    Jason Reeder

  • 0 in reply to Jason Reeder
    Expert 1280 points

    Hi Jason,
    Excellent! Thank for your explanation! I was able to understand this examples. I had no idea that XDC can be used to create virtual addresses.
    Best Regards
    Oleg

  • 0 in reply to Oleg Borovikov
    TI__Genius 10415 points

    Oleg,

    The platform file that you referenced above is how we tell the linker where we are going to create the virtual address. 

    The actual virtual address creation is accomplished by using the MPAX registers for each of the DSP cores. Documentation for the MPAX registers can be found in section 7.3 of the CorePac User Guide (http://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf). 

    The OpenMP examples use a function called initMPAX() found in the omp_1_01_03_02/packages/ti/omp/config/sysbios/preinit.c file to modify the MPAX registers and create this virtual addressing. The initMPAX function is called before the c_int00() function returns.

    Jason Reeder

  • 0 in reply to Jason Reeder
    Expert 1280 points

    Hi Jason,

    I am dealing with a very complex computational task, it requires a lot of resources. I should have a very good knowledge about hardware and software of my TMS320C6678. Your advice is very valuable for me. I will follow them.
    Thank,

        Oleg

  • 0 in reply to Oleg Borovikov
    TI__Genius 10415 points
    As an update to this thread, we have continued to improve our implementation of OpenMP and have released these updates in a software release for KeyStone II devices. A wiki page has been created that gives instructions on how to download the new OpenMP implementation and port it to KeyStone I devices. Please find the wiki page here: processors.wiki.ti.com/.../Porting_OpenMP_2.x_to_KeyStone_1 for the porting instructions.

    Thanks,

    Jason Reeder
  • 0 in reply to Jason Reeder
    Expert 1280 points

    Hi Jason,

    Thank for your advice!

    Best regards,

       Oleg