What is the DDR3 memory speed of the EVMK2H?

John Romein

We have an EVM2KH board with a 2 GB DDR3-1333 SO DIMM. According to the Keystone DDR3 memory controller manual (SPRUGV8D), the performance counter time register (PERF_CNT_TIM) increments at half the DDR3 memory clock speed. I see that the register increases at a rate of 409.8 MHz. This is not what I expect: with DDR3-1333 memory, I expect an I/O clock of 667 MHz, and thus PERF_CNT_TIM to increase at a rate of 333 MHz. How fast is the memory, and what bandwidth should I expect?

Thanks, John

over 9 years ago

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Hello John,

I think the below thread would be helpful for you to clarify your question. Please let me know, if you have further questions.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/288732/1007592

Regards,

Senthil

0 John Romein over 9 years ago in reply to Senthilkumar Srinivasan

Intellectual 300 points

Dear Senthil,

I saw this thread before, but on our (EVMK2H) device, I see the performance counter increment at a rate of 409.8 MHz, where I expect 666.7 MHz for a DDR3-1333 module. Also, I can read/write data at a maximum speed of 6.3 GB/s in practice, where I would expect a peak bandwidth of 10.67 GB/s for DDR-3 1333 memory. Hence my question: is the DDR3 memory of the EVMK2H underclocked? PERF_CNT_TIM runs at 61% of the expected rate, and I get 59% of the expected bandwidth in practice; this can hardly be a coincidence ...

Thanks, John

0 Senthilkumar Srinivasan over 9 years ago in reply to John Romein

TI__Mastermind 43660 points

Hello John,

What is the clock frequency of your DDR PLL output ?

Have you initialized the DDR PLL properly ?

Regards,
Senthil

0 John Romein over 9 years ago in reply to Senthilkumar Srinivasan

Intellectual 300 points

Hello Senthil,

How can I check the DDR PLL frequency easily?
I did not initialize the DDR myself; this is just a stock EVMK2H board. The uboot/linux tools that you provide initialize the system.

Thanks, John

0 John Romein over 9 years ago in reply to John Romein

Intellectual 300 points

Found it:

TCI6638 EVM # getclk 3
clock index [3] - frequency 400000000

Can/should I change this? How?

Thanks, John

0 Titusrathinaraj Stalin over 9 years ago in reply to John Romein

TI__Guru** 116100 points

Hi John,

Yes, you are right. "getclk 3" would read the DDR3A's PLL clock

You can refer to the following u-boot source file for DDR3A PLL clock definitions.

u-boot-keystone/arch/arm/cpu/armv7/keystone/clock-k2hk.c

enum clk_e {

core_pll_clk,

pass_pll_clk,

tetris_pll_clk,

ddr3a_pll_clk,

ddr3b_pll_clk,

sys_clk0_clk,

sys_clk0_1_clk,

static unsigned long pll_freq_get(int pll)

{

switch (pll) {

case PASS_PLL:

ret = external_clk[pa_clk];

reg = K2HK_PASSPLLCTL0;

break;

case TETRIS_PLL:

ret = external_clk[tetris_clk];

reg = K2HK_ARMPLLCTL0;

break;

case DDR3A_PLL:

ret = external_clk[ddr3a_clk];

reg = K2HK_DDR3APLLCTL0;

break;

case DDR3B_PLL:

ret = external_clk[ddr3b_clk];

reg = K2HK_DDR3BPLLCTL0;

./board/ti/ks2_evm/board_k2hk.c

unsigned int external_clk[ext_clk_count] = {

[sys_clk] = 122880000,

[alt_core_clk] = 125000000,

[pa_clk] = 122880000,

[tetris_clk] = 125000000,

[ddr3a_clk] = 100000000,

[ddr3b_clk] = 100000000,

[mcm_clk] = 312500000,

[pcie_clk] = 100000000,

[sgmii_srio_clk] = 156250000,

[xgmii_clk] = 156250000,

[usb_clk] = 100000000,

[rp1_clk] = 123456789 /* TODO: cannot find

what is that */

};

0 Raja over 9 years ago in reply to Titusrathinaraj Stalin

TI__Guru* 81335 points

Hi John,
Please help us to close this thread. Thank you.

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What is the DDR3 memory speed of the EVMK2H?