problem with mcsBP events on edma. C6657 platform

Hello,

We use the TI EVM board TMS320C6657 . I have already gone throught the example that you refer.

But because of the fact that we want to transfer a software that runs in an older dsp to the new one, is very difficult to use this mcbsp driver. We try to understand the way that works and to adjust this to our software.

When the MCSBP starts,  the value of the SPCR changes from  0x02F18031 to 0x02F38031. Thismeans that the transmitter is ready to transmit. But no event comes to interrupt.

For this reason we asked you to provide us support.

Moreover  is it necessary to   enable the TCINTEN?

Thank you in advance

George 

Hi George,

Thanks for your update.

If the transfer completion interrupts are not asserted, kindly ensure the following:

1. The interrupt generation is enabled in the OPT of the associated PaRAM set (TCINTEN =1 and/or ITCINTEN = 1)

2. The interrupts are enabled in the EDMA3 Channel Controller, via the Interrupt Enable Registers (IER/IERH)

3. The corresponding interrupts are enabled in the device interrupt controller

4. The set interrupts are cleared in the interrupt pending registers (IPR/IPRH) before exiting the transfer completion interrupt service routine (ISR)

5. If working with shadow region interrupts, make sure that the DMA Region Access registers (DRAE/DRAEH) are set up properly, because the DRAE/DRAEH registers act as secondary enables for shadow region completion interrupts, along with the IER/IERH registers.

For instance, if the PaRAM set associated with Channel 0 returns a completion code of 63 (OPT.TCC=63), ensure that DRAEH.E63 is also set for a shadow region completion interrupt because the interrupt pending register bit set will be IPRH.I63 (not IPR.I0)

Thanks & regards,

Sivaraj K

-------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question.

-------------------------------------------------------------------------------------------------------

Hello ,


Bellow I give a brief description again about the problem that I face

I want to setup the edma in order to listen MCSBP events .

The setup is the following for the EDMA

//McBSP0 Rx
chId = EDMA3_DRV_HW_CHANNEL_MCBSP0_RX //event 36;
chId1 = EDMA3_DRV_LINK_CHANNEL;
chId2 = EDMA3_DRV_LINK_CHANNEL;
tcc = EDMA3_DRV_HW_CHANNEL_MCBSP0_RX;

result = EDMA3_DRV_requestChannel (hEdma[0], &chId, &tcc, (EDMA3_RM_EventQueue)0, &QDMA_perHwiFxn, &qdmaPerChannels[0].line);
result |= EDMA3_DRV_requestChannel (hEdma[0], &chId1,&tcc, (EDMA3_RM_EventQueue)0, &QDMA_perHwiFxn, &qdmaPerChannels[0].line);
result |= EDMA3_DRV_requestChannel (hEdma[0], &chId2,&tcc, (EDMA3_RM_EventQueue)0, &QDMA_perHwiFxn, &qdmaPerChannels[0].line);

paramSet.opt = 0x00100000 | (tcc<<12);
paramSet.srcAddr = mcbsp->drr; //DRR of McBSP0
paramSet.destAddr = (Uint32) &qdmaPingIn0;
paramSet.aCnt = 1;
paramSet.bCnt = numTsl;
paramSet.cCnt = PCM_SAMPLES_PER_MS;
paramSet.bCntReload = numTsl;
paramSet.srcBIdx = 0;
paramSet.destBIdx = 1;
paramSet.srcCIdx = 0;
paramSet.destCIdx = 1;

result |= EDMA3_DRV_clearErrorBits (hEdma[0], chId);
result |= EDMA3_DRV_setPaRAM(hEdma[0], chId, &paramSet);
result |= EDMA3_DRV_setPaRAM(hEdma[0], chId2, &paramSet);
paramSet.destAddr = (Uint32) &qdmaPongIn0;
result |= EDMA3_DRV_setPaRAM(hEdma[0], chId1, &paramSet);

result |= EDMA3_DRV_linkChannel (hEdma[0], chId, chId1);
result |= EDMA3_DRV_linkChannel (hEdma[0], chId1, chId2);
result |= EDMA3_DRV_linkChannel (hEdma[0], chId2, chId1);
result |= EDMA3_DRV_enableTransfer (hEdma[0], chId, EDMA3_DRV_TRIG_MODE_EVENT);

qdmaPerChannels[0].linkChan_1_Rx = chId1;
qdmaPerChannels[0].linkChan_2_Rx = chId2;

//McBSP0 Tx
chId = EDMA3_DRV_HW_CHANNEL_MCBSP0_TX //event 37;
chId1 = EDMA3_DRV_LINK_CHANNEL;
chId2 = EDMA3_DRV_LINK_CHANNEL;
tcc = EDMA3_DRV_HW_CHANNEL_MCBSP0_TX;

result |= EDMA3_DRV_requestChannel (hEdma[0], &chId, &tcc, (EDMA3_RM_EventQueue)0, &QDMA_perHwiFxn, &qdmaPerChannels[0].line);
result |= EDMA3_DRV_requestChannel (hEdma[0], &chId1, &tcc, (EDMA3_RM_EventQueue)0, &QDMA_perHwiFxn, &qdmaPerChannels[0].line);
result |= EDMA3_DRV_requestChannel (hEdma[0], &chId2, &tcc, (EDMA3_RM_EventQueue)0, &QDMA_perHwiFxn, &qdmaPerChannels[0].line);

paramSet.opt = 0x00100000 | (tcc<<12);

paramSet.srcAddr = (Uint32) &qdmaPingOut0;
paramSet.destAddr = mcbsp->dxr; //DXR of McBSP0
paramSet.aCnt = 1;
paramSet.bCnt = numTsl;
paramSet.cCnt = PCM_SAMPLES_PER_MS;
paramSet.bCntReload = numTsl;
paramSet.srcBIdx = 1;
paramSet.destBIdx = 0;
paramSet.srcCIdx = 1;
paramSet.destCIdx = 0;

result |= EDMA3_DRV_clearErrorBits (hEdma[0], chId);
result |= EDMA3_DRV_setPaRAM(hEdma[0], chId, &paramSet);
result |= EDMA3_DRV_setPaRAM(hEdma[0], chId2, &paramSet);
paramSet.srcAddr = (Uint32) &qdmaPongOut0;
result |= EDMA3_DRV_setPaRAM(hEdma[0], chId1, &paramSet);

result |= EDMA3_DRV_linkChannel (hEdma[0], chId, chId1);
result |= EDMA3_DRV_linkChannel (hEdma[0], chId1, chId2);
result |= EDMA3_DRV_linkChannel (hEdma[0], chId2, chId1);
result |= EDMA3_DRV_enableTransfer (hEdma[0], chId, EDMA3_DRV_TRIG_MODE_EVENT);

When the setup finishes the DRAEH has the value 0x30 (36 and 37 logical channels are enabled) and the IER has the same value

The IRH register has the value 0

The opt.tcc has also been setup correctly for the param set 36 and 37.

The IER has also the value 0x30

I think that all the value that you refereed in your previous emails are correclty setup.

But no interrupt happens.

The configuration file that I use is the same as the configuration file under pdkc6657 for the digital loopback example



The setup of the MCSBP that is preced the EDMA configuration is the following

mcbsp->spcr = MCBSP_SPCR_INIT;

mcbsp->pcr = 0

mcbsp->rcere0=0xFFFFFFFF;

mcbsp->xcere0=0xFFFFFFFF; //enable all tx channels
mcbsp->xcere1=0xFFFFFFFF; //enable all tx channels

//wait at least 2 PCM clock cycles for internal syncronization
Task_sleep( 2 );
//set the XRST bit to enable the transmitter
mcbsp->spcr |= MCBSP_SPCR_XRUN;
//wait at least 2 PCM clock cycles for internal syncronization
Task_sleep( 2 );

//disable Tx/Rx to clear a XSYNCERR, that might have occured. (see also sprugj6c for more details)
mcbsp->spcr = mcbsp->spcr & (~MCBSP_SPCR_XRUN);

This piece of code is after the edma setup
mcbsp->pcr = 0x00000F00;
mcbsp->srgr = 0x20000048;//300MHz
mcbsp->spcr = 0x02F18031;

After this point the value of the spcr changes to 0x02F318031 and stucks.

The code for interrupts is the same as the code that is included in the \edma3_lld_02_11_05_02\packages\ti\sdo\edma3\drv\sample\src.

In the system register window the interrupts 7 8 9 10 11 are enabled

Is something missing?

Could you plese help me .

PS. For the digital loopback example for the  TMS32C6657 board  the function  platform_fpgaWriteConfigReg is called before the MCSBP   is initialized. Is this necessary?

Best regards

George

This is a demo project.

Hi,

Please ensure the set interrupts are cleared in interrupt pending register (IPR/IPRH) before exiting the transfer completion ISR.  

Kindly check the transfer completion code returns from the PaRAM set assoicated with the requested channel is the same which has been set for DMA Region Access registers (DRAE/DRAEH) for the shadow region completion interrupt.

Also Please check whether TCINTEN =1 is enabled in the OPT of the associated PaRAM set  as well appropriate IER/IERH's are enabled in the EDMA CC and the corresponding interrupts are enabled in the device interupt controller.

Thanks & regards,

Sivaraj K

-------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question.

-------------------------------------------------------------------------------------------------------

Hello,
We have checked the registers that you referred and all seems fine. But we checked the register TCSTAT register and the value of this register never changes
It seems that the event TX or RX  never trigerrs  the MCSBP event.

P.S the manual_event triggers the edma

Best regards,
George

George,

giorgos tsoumplekas said:

It seems that the event TX or RX  never trigerrs  the MCSBP event.

- On the EDMA side:

The different events to enable seems the one that Sivaraj highlighted.

To get familiar with EDMA architecture:
http://processors.wiki.ti.com/index.php/EDMA3
http://processors.wiki.ti.com/index.php/Programming_EDMA_without_EDMA3LLD_package
Also there is an EDMA example using CSL API that is provided at the below link:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/177116/1143546
It does not use McBSP but it enable to see a step by step config using CSL APIs and generate an EDMA interrupt.

A.

George,

a) I just quickly looked at the PCM_hwCfgMcBSP() fct. It does not seem that you follow exactly the init procedure of section 2.12.1 of MCBSP UG - SPRUHH0.

To start with please try to stick to the init procedure documented.

b) - You could used the CSL register layer to control the McBSP so that you do not have to maitain your own code.

We do not have mcBSP example for C665x that uses the CSL register layer. Still I enclosed a CEL register layer example for DM643x just to show you the usage of the different MACRO.
This example does not follow the proper sequence described in section  2.12.1 but you can modify it.

-also this example show a basic internal loopback example (internal TX -> RX using CPU polling) which is probably the best way to start with as it does not depend on external timings.
Can you try to modify it, compiler and run it on your target?

When you have it working you can merge it with the EDMA example I pointed you to in the previous post.

A.

//dvsdk_1_11_00_00_DM648\pspdrivers_1_10_00\packages\ti\sdo\pspdrivers\soc\dm6437\examples\mcbsp\src
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006, 2007
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 *  ============================================================================
 */

/** ============================================================================
 *   @brief A simple example to demonstrate CSL 3.x MCBSP register layer usage.
 *
 *   @file  mcbsp_example.c
 *
 *   <b> Example Description </b>
 *   @verbatim
     This example configures MCBSP0 in 32 bit loopback mode and uses software 
     polling to transmit and receive 32bit words. Four 32 bit words are 
     transmitted and received and the results are verified.  A pass\fail 
     test status is returned from main.     
     @endverbatim
 *
 *      
 *   <b> Procedure to run the example </b>
 *   @verbatim
     1. Configure the CCS setup to work with the emulator being used
     2. Please refer CCS manual for setup configuration and loading 
        proper GEL file
     3. Launch CCS window
     4. Open project Mcbsp_example.pjt
     5. Build the project and load the .out file of the project.
     @endverbatim
 *
 * =============================================================================
 **/

#include <csl_types.h>
#include <soc.h>
#include <cslr_sys.h>
#include <cslr_mcbsp.h>
#include <stdio.h>
#include <cslr_psc.h>
#define NUM_WORDS   4

static void device_init(void); 
static void init_mcbsp(void);   
static int test_mcbsp(void);   
 

CSL_McbspRegsOvly mcbspRegs = (CSL_McbspRegsOvly)CSL_MCBSP_0_REGS;

int main (void) 
{
  //enable mcbsp0 in power and sleep controller
  device_init(); 
  
  //setup mcbsp registers and start mcbsp running 
  init_mcbsp();
  
  //test loopback, returns 0 for pass and 1 for fail 
  return(test_mcbsp());
}

void init_mcbsp(void)
{
  //serial port control register SPCR
  mcbspRegs->SPCR = CSL_FMKT(MCBSP_SPCR_DLB,ENABLE);    //enable loopback mode     
                 
  // receive control register                
  mcbspRegs->RCR = CSL_FMKT(MCBSP_RCR_RWDLEN1,32BIT);   //receive word 32bit 
  
  //transmit control register
  mcbspRegs->XCR = CSL_FMKT(MCBSP_XCR_XWDLEN1,32BIT);   //trans word 32bit
  
  //sample rate generator SRGR
  mcbspRegs->SRGR = CSL_FMKT(MCBSP_SRGR_CLKSM,INTERNAL) //internal clock
                  | CSL_FMK(MCBSP_SRGR_FPER,63)         //frame period
                  | CSL_FMK(MCBSP_SRGR_FWID,31)         //frame width
                  | CSL_FMK(MCBSP_SRGR_CLKGDV,15);      //clock divider value

  //pin control register
  mcbspRegs->PCR = CSL_FMKT(MCBSP_PCR_FSXM,INTERNAL)    //internal frame sync
                 | CSL_FMKT(MCBSP_PCR_FSRM,INTERNAL)    //internal fram sync
                 | CSL_FMKT(MCBSP_PCR_CLKXM,OUTPUT);    //trans clock mode
        
                 
  //start the mcbsp running
  CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_RRST,ENABLE);    //receiver enable
  CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_XRST,ENABLE);    //transmitter enable
  CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_GRST,CLKG);      //SRGR out of reset
  CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_FRST,FSG);       //enable frame sync
}

int test_mcbsp(void)
{
    int i;
    Uint32 trans_val[NUM_WORDS] = {0x12345678,0x87654321,0x11223344,0x55667788};
    Uint32 rec_val[NUM_WORDS];

    printf("\nTesting mcbsp loopback\n\n");

    for(i=0;i<(sizeof(trans_val)/sizeof(trans_val[0]));i++) 
    {
        //poll transmitter ready
        while(CSL_FEXT(mcbspRegs->SPCR,MCBSP_SPCR_XRDY)
             != CSL_MCBSP_SPCR_XRDY_YES);

        //write to transmit register
        mcbspRegs->DXR = trans_val[i];

        //poll receiver is ready
        while(CSL_FEXT(mcbspRegs->SPCR,MCBSP_SPCR_RRDY)
             != CSL_MCBSP_SPCR_RRDY_YES);

        //read receive register
        rec_val[i] = mcbspRegs->DRR;
    }

    //check results
    for(i=0;i<(sizeof(trans_val)/sizeof(trans_val[0]));i++) 
    {
        if(trans_val[i]==rec_val[i])
            printf("transmit: 0x%x   receive: 0x%x\n",trans_val[i],rec_val[i]);
        else
           {
             printf(" error\n");
             printf("\nMCBSP Loopback Test:  FAILED\n");
             return(1);
           }
    }

    printf("\nMCBSP Loopback Test:  PASSED\n");
    
    return(0);
}

void device_init(void) 
{
  
  CSL_PscRegsOvly pscRegs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;

  // deassert MCBSP0 local PSC reset and set NEXT state to ENABLE
  pscRegs->MDCTL[CSL_PSC_MCBSP0] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE )
                                 | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
 
  //move MCBSP0 PSC to Next state
  pscRegs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );
 
  //wait for transition
  while ( CSL_FEXT( pscRegs->MDSTAT[CSL_PSC_MCBSP0], PSC_MDSTAT_STATE )
          != CSL_PSC_MDSTAT_STATE_ENABLE );
 
}
 

Hello,

Thank you for the answer.

I mean that the XRDY  bit in SPCR is set correctly. I checked the MCSBSP in pooling mode with CPU and works. 

Regarding the code that you mentioned for the EDMA ,  I am little confused.

I cannot understand what this function CSL_intcOpen  do

What is the reference table for this function?
Can you please give me an example?

Where I should setup that the EDMA is waiting for a MCSBP event?

George

Hi Giorgos,

giorgos tsoumplekas said:

I cannot understand what this function CSL_intcOpen  do

The INTC module has got a dispatcher and it maintains a table for the mapping between the interrupt src to CPU and the different events. Mapping is done using CSL_intcOpen() fct.
The below document does provide info on the CSL 2.x (used in C641x, DM642, ..etc) to CSL 3.x (used in C66x) migration. For INTC see section 6 and specifically 6.5 to get an understanding on the dispatcher:
http://www.ti.com/lit/an/spraa10/spraa10.pdf

giorgos tsoumplekas said:

Where I should setup that the EDMA is waiting for a MCSBP event?

a) Events to EDMA:
Each peripheral events are tied to a given EDMA channel so you need to use the according EDMA channel for the according McBSP event. RCV and TX events are different events so you need to use different channels.
Then the peripheral events should be enabled in the EER.

See slides 95, 13 and 27 of the below presentation:
http://processors.wiki.ti.com/images/b/b8/Eindhoven_JAN_12-10_IntroTo_Edma.pdf?keyMatch=TCINTEN&tisearch=Search-EN

As a test you can trigger manually the EDMA via the ESR register. This is a good test to do to check that the EDMA operate accordingly.


b) For EDMA to trigger interrupts:
The 2 key bitfield are TCC and TCINTEN. See slide 98 of the previous presentation.


A.