C6678 IPC and MSMC

Hi Murad,
There were many threads in e2e discussed about ipc_attach() sync issue. Please check weather below threads helps to solve the issue,
e2e.ti.com/.../386750
e2e.ti.com/.../386750
e2e.ti.com/.../1230097

Thank you.

Thank you Rajasekaran,
I did read the above threads before. I got MessageQ running on 8 cores using the example project in IPC, but when I used my project with my full code, it doesn't work. couple questions:
1- when you load lets say same .out (same .cfg and memory map) on different cores and each uses the MSM/DDR3, who manage putting the code in different locations in the MSM/DDR3 ?
2- if I only want to use 3 cores and use Ipc.procSync = Ipc.ProcSync_ALL;
will the following changes to the .cfg allows me to use 3 (core 0, 1, 2) of the C6678 cores
core 0:
MultiProc.numProcessors = 3;
MultiProc.setConfig("CORE0", ["CORE0", "CORE1", "CORE2"]);

core 1:
MultiProc.numProcessors = 3;
MultiProc.setConfig("CORE1", ["CORE0", "CORE1", "CORE2"]);

core 2:
MultiProc.numProcessors = 3;
MultiProc.setConfig("CORE2", ["CORE0", "CORE1", "CORE2"]);

Also,

Can I use the same call back for Event Notify module with 2 different procId as follows:

Void Outbound_monitoring_cbFxn(UInt16 procId, UInt16 lineId,

UInt32 eventId, UArg arg, UInt32 payload)

{

switch (payload)

{

case P25T_OUTBOUND_DETECTED:

p25TchanStatus = 1;

p25TchanStatusLsm = 1;

break;

}

}

int main()

{

int status;

   /*

    *  Ipc_start() calls Ipc_attach() to synchronize all remote processors

    *  because 'Ipc.procSync' is set to 'Ipc.ProcSync_ALL' in *.cfg

    */

   Ipc_start();

// while (Ipc_attach(1) < 0) {

// platform_delay(1);

//    }

//

// while (Ipc_attach(2) < 0) {

// platform_delay(1);

//    }

   status = Notify_registerEvent(1, INTERRUPT_LINE, OUTBOUND_MONITORING_EVENTID, (Notify_FnNotifyCbck)Outbound_monitoring_cbFxn, NULL);

   if (status < 0) {

       System_abort("Notify_registerEvent failed\n");

   }

   status = Notify_registerEvent(2, INTERRUPT_LINE, OUTBOUND_MONITORING_EVENTID, (Notify_FnNotifyCbck)Outbound_monitoring_cbFxn, NULL);

   if (status < 0) {

       System_abort("Notify_registerEvent failed\n");

   }

/* Start the BIOS 6 Scheduler - it will kick off our main thread mainStart_task_Fxn() */

BIOS_start();

}

I disables the Notify module to just make sure the cores sync using Ipc.ProcSync_ALL...but now I get the following output at the console???

[C66xx_1] A0=0x8026eeb8 A1=0x1
A2=0xf A3=0x0
A4=0x0 A5=0x0
A6=0x0 A7=0x0
A8=0x1 A9=0x0
A10=0x0 A11=0x0
A12=0x0 A13=0x0
A14=0x0 A15=0x0
A16=0x1 A17=0x2
A18=0x0 A19=0x120
A20=0x0 A21=0xc1047bc
A22=0x833f00 A23=0x2
A24=0xc103f14 A25=0x0
A26=0xc103ee4 A27=0x20
A28=0x430e100d A29=0xc01026db
A30=0x8100200 A31=0x3222428
B0=0x1404b05 B1=0x6311018
B2=0x24400004 B3=0x2002952d
B4=0x1181220 B5=0x8023a6e0
B6=0x20 B7=0xc302f0c
B8=0x0 B9=0x0
B10=0x0 B11=0x0
B12=0x801f36b0 B13=0x80204f88
B14=0x1 B15=0xc1047b8
B16=0x80204f80 B17=0x80200444
B18=0x8023aa62 B19=0xffffffbe
B20=0x10641 B21=0x1
B22=0x0 B23=0x40000000
B24=0x82c3d8 B25=0x464240
B26=0x840400 B27=0xe025140a
B28=0x4a802284 B29=0x0
B30=0xc305300 B31=0xc103dd4
NTSR=0x10000
ITSR=0x80008498
IRP=0x0
SSR=0x0
[C66xx_0] A0=0x0 A1=0x0
[C66xx_1] AMR=0x0
[C66xx_0] A2=0x1 A3=0x0
[C66xx_1] RILC=0x15000102
[C66xx_0] A4=0x0 A5=0x815d21dc
[C66xx_1] ILC=0x0
[C66xx_0] A6=0x0 A7=0x0
[C66xx_1] Exception at 0x0
[C66xx_0] A8=0x0 A9=0x2
[C66xx_1] EFR=0x2 NRP=0x0
[C66xx_0] A10=0x0 A11=0x1c
[C66xx_1] Internal exception: IERR=0x1
[C66xx_0] A12=0x14 A13=0xffffffff
[C66xx_1] Instruction fetch exception
[C66xx_0] A14=0x0 A15=0x0
[C66xx_1] ti.sysbios.family.c64p.Exception: line 255: E_exceptionMin: pc = 0x00000000, sp = 0x0c1047b8.
[C66xx_0] A16=0xc05693c A17=0x0
[C66xx_1] To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePrint = true;'
[C66xx_0] A18=0xc05690c A19=0x20
[C66xx_1] xdc.runtime.Error.raise: terminating execution
[C66xx_0] A20=0x0 A21=0x0
A22=0x0 A23=0x0
A24=0x0 A25=0x0
A26=0x0 A27=0x2005000
A28=0x0 A29=0x43
A30=0x8 A31=0x0
B0=0x1 B1=0x0
B2=0x0 B3=0x81569824
B4=0xffffffff B5=0x15000103
B6=0x14 B7=0x815d23a8
B8=0xffffffff B9=0x4
B10=0x0 B11=0xc056a9c
B12=0x0 B13=0x0
B14=0x815d3a98 B15=0xc056a70
B16=0xc0568a8 B17=0x81426538
B18=0x40 B19=0x78
B20=0x0 B21=0x2e2
B22=0x2e20000 B23=0x0
B24=0x0 B25=0x3000
B26=0x3000 B27=0x0
B28=0x0 B29=0x0
B30=0x81452910 B31=0x0
NTSR=0x1000f
ITSR=0x400f
IRP=0x8154b520
SSR=0x0
AMR=0x0
RILC=0x0
ILC=0x0
Exception at 0x0
EFR=0x2 NRP=0x0
Internal exception: IERR=0x1
Instruction fetch exception
ti.sysbios.family.c64p.Exception: line 255: E_exceptionMin: pc = 0x00000000, sp = 0x0c056a70.
To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePrint = true;'
xdc.runtime.Error.raise: terminating execution

I disabled the MessageQ and NOW I am only trying to sync 3 cores...AND NO LUCK...The above console printout is gone but the cores never pass ipc_start(). Also increased the heap size but nothing changed
Memory.defaultHeapSize = 0x8000000;//MQ was 0x10000;

Note: I was able to get 8 cores to sync using MessageQ example but I am trying to at least sync now with 3 cores having my actual project code!

I did split the DDR3 among the 3 cores and still doesn't sync with 3 cores...it only work with 2 cores

What happened to TI customer service!!!...I used to get replies within a day or two...now I have posts waiting for reply for more than a month...Am I missing anything!!!

Hi Murad,

 

Sorry for the inconvenience caused due to delay.

We will look into it and get back.

 

Regards,

Shankari

since I am using DDR3, do I need to call platform_init in cores other than core 0

sFlags.pll = 0; /* PLLs for clocking */
sFlags.ddr = 0; /* External memory */
sFlags.tcsl = 1; /* Time stamp counter */
sFlags.phy = 1; /* Ethernet */
sFlags.ecc = 0; /* Memory ECC */

sConfig.pllm = 0; /* Use libraries default clock divisor */

pform_status = platform_init(&sFlags, &sConfig);

DDR3 only needs to be configured once.

Kind regards,
one and zero

Hi Murad,

Sorry for the inconvenience caused due to delay.
As One and zero stated, yes DDR initialization must be done only once through core0 and other cores could use DDR.

This "EVM_init" function (DDR init) get callled while loading "master" code.

Say, if you want to run 3 different .out in 3 cores ,"master" "slave" and "your new IPC code"
Could you attach the ".cfg" of other .out

How did you manage the memory segments for the new IPC code ?

2- if I only want to use 3 cores and use Ipc.procSync = Ipc.ProcSync_ALL;
will the following changes to the .cfg allows me to use 3 (core 0, 1, 2) of the C6678 cores
core 0:
MultiProc.numProcessors = 3;
MultiProc.setConfig("CORE0", ["CORE0", "CORE1", "CORE2"]);

core 1:
MultiProc.numProcessors = 3;
MultiProc.setConfig("CORE1", ["CORE0", "CORE1", "CORE2"]);

core 2:
MultiProc.numProcessors = 3;
MultiProc.setConfig("CORE2", ["CORE0", "CORE1", "CORE2"]);

This configuration seems to be good.

Yes, you can use "Ipc.procSync = Ipc.ProcSync_ALL" for running 3 .out on 3 cores.
If you use " Ipc.ProcSync_ALL" then you no need to call "Ipc_attach" manually.

Have you gone through all the modules from IPC ?

processors.wiki.ti.com/.../Ipc_Module
processors.wiki.ti.com/.../IPC_User%27s_Guide

I did read the above threads before. I got MessageQ running on 8 cores using the example project in IPC, but when I used my project with my full code, it doesn't work. couple questions:

Could you attach the code and have you modifed the .cfg accordingly ?

Thanks Shankari for the reply,

I did read the above documents and more.

3 cores sync using Ipc.ProcSync_ALL and message seems to work fine...but when I register Notify from cores 1 and 2 with core 0, they code stop running...when I only register Notify 1 in core 0, thengs run ok.

My memory map:

        name            origin    length      

----------------------  --------  ---------  --------  

 L2SRAM                00800000   00080000

 MSMCSRAM_MASTER       0c000000   00100000  

 MSMCSRAM_SLAVE        0c100000   00100000  

 MSMCSRAM_IPC          0c200000   00200000  

 DDR3P25T              80000000   02000000

 DDR3P25C              82000000   02000000  

 DDR3MOTO              84000000   02000000  

 DDR3                  86000000   1fffffff

cores 0,1,2  .cfg are attachedDIAGNOSTX_MASTER.cfgP25T_INBOUND_DIAGNOSTX.cfgP25C_INBOUND_DIAGNOSTX.cfg

main() for the 3 cores:

int main()

{

int status;

status = Ipc_start();

   if (status < 0) {

       System_abort("Ipc_start failed\n");

   }

BIOS_start();

}

the Notify attach in core 0 is:

if ENABLE_NOTIFY_CORE2 is defined, the code doesn't run...if not defined or If I change core id to 1 instead of 2, code works???

Void NotifyAttachFxn(UArg arg)

{

int status;

   status = Notify_registerEvent(1, INTERRUPT_LINE, OUTBOUND_MONITORING_EVENTID, (Notify_FnNotifyCbck)Outbound_monitoring_cbFxn, NULL);

   if (status < 0) {

       System_abort("Notify_registerEvent failed\n");

   }

#ifdef ENABLE_NOTIFY_CORE2

status = Notify_registerEvent(2, INTERRUPT_LINE, OUTBOUND_MONITORING_EVENTID, (Notify_FnNotifyCbck)Outbound_monitoring_cbFxn1, NULL);

if (status < 0) {

System_abort("Notify_registerEvent failed\n");

}

#endif

}

Void NotifyDetachFxn(UArg arg)

{

//TBD

System_abort("MQ: Notify Detach\n");

}