hello,
the following figure shows TLP and DLLP Structure at the Pysical Layer in PCIe architecture (Gen 2.0).
START (1 Byte) | SEQUENCE ID (2 Bytes) | HEADER (12/16 Bytes) | DATA PAYLOAD | ECRC (4 Bytes) | LCRC (4 Bytes) | END (1 Byte) |
START (1 Byte) | DLLP (6 Bytes) | END (1 Byte) |
I want to transfer data with CPU (32 bits addressing) from DSP TMS320C6678 (RC) to another DSP TMS320C6678 (EP), therefore the maximum Data Payload is 4 Bytes and the header is encoding to 12 Bytes.
so, I want to calculate the maximum throughput efficiency in both memory read and memory write using CPU transfert.
I proceed as follows:
maximum throughput efficiency % = ( Data payload size ) / ( Data payload size + overhead )
* Data Payload size is 4 Bytes
the problem is at the "overhead" ; if I consider the DLLP, I get 32 Bytes else i get 24 Bytes.
So :
*maximum throughput efficiency (With DLLP) % = 11.11 %
*maximum throughput efficiency (Without DLLP) % = 14.28 %
I found the following two documents TI :
1) C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\docs\ ==> page 11 ==> it does not use DLLP
2) Keystone PCI expres usage ==> page 11 ==> it use DLLP but ignored ECRC field
which of these two values I have to take , with or without DLLP and why ?