Throughput Memory Write RC to EP using CPU _ PCIe

Hi,

In general, you need to set PCIE to GEN2 with 2 lanes and use EDMA to get the best throughput. It should not take that long to transfer 64B to 1MB data.

What is the program running on DSP side? Is it the PCIe example project in MCSDK/PDK package?

Thanks,

Hi,
I used PCIe GEN2 with 2lanes.
No, I do not want to use EDMA, I want to know the behavior of the throughput using CPU.
yes , it is the PCIe example project in MCSDK/PDK package.


Sincerely,

Zakaria.

Hi,

Without using EDMA means, you got very less PCIe throughput (up to 150MBps). For testing it should be ok. Better to use EDMA for PCIe transfer on your main application to get the best throughput values.

Eric already explained the same test case on below thread. Please take a look at this thread, it should be help you.
e2e.ti.com/.../927081

e2e.ti.com/.../107676

Thanks,

Hi,

the peak in data size 16Byte bothers me , i do not know why !! , Normally, the throughput must be maximum in data size 4 Byte not in 16 Byte !!
is it logical ??

Sincerely,

Zakaria.

Have you got the same results at multiple test?

It is not a expected results.

Thanks,

Hi,

Yes , I did several test ! but I always find the same result.

Sincerely,

Zakaria.

Hi,

Have you using MCSDK PCIe example code for your testing? How to modified the payload size on your test code?

what is the intention for this testing?

Share your test code, i will try to reproduce your issue.

Thanks,

Hi,

Yes, I use the MCSDK PCIe example code .

this is the code of transaction memory Write with CPU ( data size 4 MB) :

VOID App_Mwr_CPU(UINT32* src_data,UINT32* dst_data)
{

bufLimit=12; // 4B^11=4MB
Ncycle_RC=0;
Nafter_RC=0;
Nbefore_RC=0;
CSL_tscEnable();

for(j=1;j<bufLimit;j++){

pcie_SIZE*=4;
Ncycle_RC=0;

Nbefore_RC=CSL_tscRead ();
//PCIe transfer using CPU
for (i=0; i<pcie_SIZE/4; i++)
{
*((volatile UINT32 *)dst_data + i) = src_data[i];
}

Nafter_RC=CSL_tscRead ();
Ncycle_RC+=Nafter_RC-Nbefore_RC;



cpu_value_tab[j]=Ncycle_RC;
pcie_SIZE_tab[j]=pcie_SIZE;

}

for(j=1;j<bufLimit;j++){
printf("cpu_value[%lld]=%lld cycles\n",pcie_SIZE_tab[j],cpu_value_tab[j]);
}
}


I want an explanation of the values in the transitional regime, exactly in data size { 4 , 16 , 64 , 256 }


Sincerely,

Zakaria.