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how to change 'priority 'of SRIO message packet , why the 'prio' of sent packet is 0'b11

Other Parts Discussed in Thread: TMS320C6678

dear experts!

I am using the "srio_multicoreloopbackexampleProject ",with some modification I can send message from DSP to FPGA by calling srio_socksend() function.

but the 'prio' field of FPGA received packet is 11. through SRIO protocol,the priority of request packet is 0~2,it shouldn't use 3.

how do change the priority of this message packet!

from FPGA side ,through srio ip,we can capture the packet from dsp.  the header is 00b06ff000000011.

in which b is ftype massage ,6 indicates priority is 11,ff indicates the size-1 .

i don't know how to change the packet 's priority from DSP side ?

many thanks!

kind regards!

li tian

  • Li Tian,
    Aalways provide below information when you start a new thread,
    1. DSP Part number
    2. MCSDK version
    3. EVM or Custom Board
    etc.
    Thank you.
  • thanks

    Rajasekaran K

    information needed are as follows

    1, TMS320C6678

    2, mcsdk_2_01_02_06

    3, Custom Board

    By the way , I have solved this problem.

    by modifying the driver code as following mentioned.

    in c:\ti\pdk_c6678_1_1_2_6\packages\ti\drv\srio\src\srio_drv.c

    line 1747:

    {

           txCfg.priority = 0;

    }

    I modified this to : txCfg.priority = 3;

    It corresponding to RIO_TX_QUEUE_SCH_INFO.

    txCfg.priority = 0     corresponds RIO_TX_QUEUE_SCH_INFO.prio    3

    txCfg.priority = 1     corresponds RIO_TX_QUEUE_SCH_INFO.prio   2

    txCfg.priority = 2     corresponds RIO_TX_QUEUE_SCH_INFO.prio    1

    txCfg.priority = 3     corresponds RIO_TX_QUEUE_SCH_INFO.prio    0

    hardware accomplishes the translation.

    I wonder why srio driver develop set this as 0. the RIO_TX_QUEUE_SCH_INFO.prio is   3, which indicates the "prio" of packet is 0'b11, however the rapidio specification says that "priority of request packet should be 0~2, response packet priority should be request priority +1".

    I think it is a bug!

    Srio module of 6678 can receive message with prio 3. FPGA can also receive any packet without checking the prio bit, even if prio is 3 .but controller of PowerPC from Freescale performs strict checking . request packet with prio 3 can lead powerPC enters into a port-write error!

    error code is : illegal transaction decode. in the ERR_DET register.

    another way to solve this problem is to use SRIO_socket in raw mode ,instead of normal mode, you should set bAppManagedConfig=1, cfg.u.appManagedCfg.srioPktDmaTxPrio = Srio_PktDma_Prio_Low; //Srio_PktDma_Prio_Low is 3

    and manually set queue number,which can't generate interrupt. you can only polling the receiving queue .  It is said in example project"SRIO_LoopbackTestProject".

    many thanks

  • Hi,

    Thanks for your update.

    Please Take a look at below e2e thread, Travis is explained the SRIO priority.

    e2e.ti.com/.../1373426

    Thanks,