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DSP Boot RAM Memory Map in TCI6638K2K

chandan singh
Prodigy 130 points

Hi All,

I have a query ragarding the address range usable for a boot application in PCIe boot for Cores 0-7 in case of TCI6638k2k.


Setup info: TCI6638k2k
Boot method : PCIe
Document refered: datasheet SPRS836D
No IBL and DDR3 is used in our case.Needs to download an application image on Core0 L2SRAM only.

As per the datasheet table 8-1 (C66x DSP Boot RAM Memory Map),range is 0x80-0000 to 0x8f-ffff.
Then if a sample application image is to be downloaded and executed on Core0 through PCIe,
then what should be the memory range for the application to be linked(in other words,what should be the value of origin and len field in linker command file)

I have seen the example "pcieboot_ddrinit" found in mcsdk2.01.02,the address used in linker cmd file is
org = 0x10820000, len = 0x20000.
Now as per the datasheet of C6678,the address range for CorePac0 L2 SRAM is 0x10800000 - 0x1087FFFF(512K size),
and the Reserved Bootloader section in L2 SRAM as per table 2.3(SPRS691E) is 0x00872DC0 - 0x0087FFFF.

So the application address range used in case of C6678's example is fine,but in case of TCI6638K2K,what should be the range of the application. 

Thanks in advance.

Regards,
Chandan

  • 0
    TI__Mastermind 28085 points
    Hi,

    Bootloader user guide is not common for keystone 1 &2 devices, current version it support only for keystone 1 devices.

    Refer table Table 8-1 C66x DSP Boot RAM Memory Map on K2K device data manual(SPRS836D). DSP Boot RAM Memory Map is clearly explained in this table.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 130 points

    Hi Ganapathi,

    Thanks for the info.

    My understanding is that the entire C66x DSP Boot RAM Memory(range 0x80-0000 to 0x8f-ffff) is used by Rom Boot Loader(RBL).

    So if the above understanding is correct,then what memory address range,I can use for application,provided I use only Core0 L2 SRAM memory.if understanding is wrong, then please correct.

    Is there any Bootloader user guide for Keystone II devices, or any guide apart from the Chapter 8(Device Boot and Configuration) of TCI6638K2K datasheet.

    Regards,
    Chandan 

  • 0 in reply to chandan singh
    TI__Mastermind 28085 points
    Hi,

    Yes, your understanding is correct. You can use L2 SRAM memory(0x81_0000 to 0x8e_0000) for core0 .

    Bootloader user guide is not available for Keystone II devices. This document is available in feature, but i don't the exact time.

    Thanks,
  • 0
    TI__Genius 12320 points
    Hi Chandan,
    Each DSP core has available to them the L2 address range 0x80_0000-0x8f_ffff (excluding the ROM reserved fields, which may become available afterwards). So what core0 sees in this range will be different from what core3 sees.

    Each core in the system, including ARMs, can see each cores L2 by prepending these addresses with 0x1#, where # is the number of the core(0-7), so for example core3's L2 can be viewed by all other cores by address 0x1380_0000. This is also referred to as the global addresses.

    That said, If you are just running a program on core0 then you can get away with 0x80_0000, but if you are wanting to run a program on any other DSP, you will likely have to use the global addresses.

    Regards,
    Mike