Hello,
We are implementing SRIO in Xilinx Virtex-7 FPGA and trying to communicate to TMS320C6678 SRIO. The SRIO port is not operational on both sides. Each side works in loopback mode. On the TMS320C6678 the details of SW are as follows:
MCSDK PDK TMS320C6678 1.1.26
FMC667 + VC707
CCS 5.5
C6x Compiler v7.6.0
API CSL_SRIO_IsPortOk fails to connect after trying to establish a port 0 connection for a period of 5 second.
This is called from waitAllSrioPortsOperational() found in srio_laneconfig.c which a part of the TI MCSDK PDK TMS320C6678 SRIO driver package. The log message is:
Debug: Waiting for SRIO ports to be operational...
Debug: SRIO port 0 is NOT operational.
Debug: Various Register Display:
PCR: 0x02900004:0x00000005
PER_SET_CNTL: 0x02900014:0x01053800
PER_SET_CNTL1: 0x02900018:0x00000000
ERR_RST_EVNT_ICSR: 0x029001e0:0x00000000
LSUx_Reg6: 0x02900d18:0x00000010
LSU_STAT_REG0: 0x02900de8:0x00000000
SP_RT_CTL: 0x0290b124:0xff0fff00
SP_GEN_CTL: 0x0290b13c:0x40000000
Port n Control 2 CSR: 0x0290b154:0x02aa0000
SPn_ERR_STAT: 0x0290b158:0x00000001
SPn_CTL: 0x0290b15c:0xc0600001
SPx_ERR_DET: 0x0290c040:0x00000000
SPx_ERR_RATE: 0x0290c068:0x80000000
LANEn_STAT0: 0x0290e010:0x00004f08
LANEn_STAT1: 0x0290e014:0x00000000
PLM Port(n)Implement: 0x0291b080:0x00000000
PLM_SP(n)_Status: 0x0291b090:0x00000000
EM_PW_PORT_STAT: 0x0291b928:0x00000000
Debug: Various SerDes Macro Status:
SRIO_SERDES_STS: 0x02620154:0x08102041
SRIO_SERDES_CFGPLL: 0x02620360:0x00000241
Debug: SerDes Receive Channel Configuration Register[:
SRIO_SERDES_CFGRX[0]: 0x02620364:0x00440495
SRIO_SERDES_CFGRX[1]: 0x0262036c:0x00440495
SRIO_SERDES_CFGRX[2]: 0x02620374:0x00440495
SRIO_SERDES_CFGRX[3]: 0x0262037c:0x00440495
[C66xx_0] SrioDevice_init error.
On Xilinx side the SRIO core is Gen2.1. Tried in both 4-lane mode and 1-lane mode at 5Gbps.
Any suggestions?
Regards,
Ram Subramaniam