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SRIO interface not establishing link

Other Parts Discussed in Thread: TMS320C6678

Hello,

We are implementing SRIO in Xilinx Virtex-7 FPGA and trying to communicate to TMS320C6678 SRIO. The SRIO port is not operational on both sides. Each side works in loopback mode. On the TMS320C6678 the details of SW are as follows:

MCSDK PDK TMS320C6678 1.1.26

FMC667 + VC707

CCS 5.5

C6x Compiler v7.6.0

API CSL_SRIO_IsPortOk fails to connect after trying to establish a port 0 connection for a period of 5 second.

This is called from waitAllSrioPortsOperational() found in srio_laneconfig.c which a part of the TI MCSDK PDK TMS320C6678 SRIO driver package. The log message is:

Debug: Waiting for SRIO ports to be operational...

Debug: SRIO port 0 is NOT operational.

Debug: Various Register Display:

PCR: 0x02900004:0x00000005

PER_SET_CNTL: 0x02900014:0x01053800

PER_SET_CNTL1: 0x02900018:0x00000000

ERR_RST_EVNT_ICSR: 0x029001e0:0x00000000

LSUx_Reg6: 0x02900d18:0x00000010

LSU_STAT_REG0: 0x02900de8:0x00000000

SP_RT_CTL: 0x0290b124:0xff0fff00

SP_GEN_CTL: 0x0290b13c:0x40000000

Port n Control 2 CSR: 0x0290b154:0x02aa0000

SPn_ERR_STAT: 0x0290b158:0x00000001

SPn_CTL: 0x0290b15c:0xc0600001

SPx_ERR_DET: 0x0290c040:0x00000000

SPx_ERR_RATE: 0x0290c068:0x80000000

LANEn_STAT0: 0x0290e010:0x00004f08

LANEn_STAT1: 0x0290e014:0x00000000

PLM Port(n)Implement: 0x0291b080:0x00000000

PLM_SP(n)_Status: 0x0291b090:0x00000000

EM_PW_PORT_STAT: 0x0291b928:0x00000000

Debug: Various SerDes Macro Status:

SRIO_SERDES_STS: 0x02620154:0x08102041

SRIO_SERDES_CFGPLL: 0x02620360:0x00000241

Debug: SerDes Receive Channel Configuration Register[:

SRIO_SERDES_CFGRX[0]: 0x02620364:0x00440495

SRIO_SERDES_CFGRX[1]: 0x0262036c:0x00440495

SRIO_SERDES_CFGRX[2]: 0x02620374:0x00440495

SRIO_SERDES_CFGRX[3]: 0x0262037c:0x00440495

[C66xx_0] SrioDevice_init error.

On Xilinx side the SRIO core is Gen2.1. Tried in both 4-lane mode and 1-lane mode at 5Gbps.

Any suggestions?

Regards,

Ram Subramaniam

 

  • Hello Ram,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    We will get back to you on the above query shortly. Thank you for your patience.

  • Hi,

    Based on your debug log the SRIO Input and output ports are not initialized. Have you validated the hardware connection between DSP and FPGA?

    In your custom board SRIO lanes are directly connect or using SRIO switch. Have you using TI provide example code for your testing? If yes, please share the project name.

    Thanks,
  • I am working with Ram on bring up SRIO link between the Vertex 7 (vc707) and FMC667 (6678) daughter card. Our base line is from C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\srio\test\tput_benchmarking project. We were able to get SRIO port 0 to connect between the FPGA and DSP after hard coding the SRIO PLL value to 0x229 and rx/txConfig to 0x00440485. We had to make these change to get the 6678 DSP with core clock of 1.25MHZ to lock the PLL when using the FMC667 250MHz SRIO Ref clock. Now we are having problems with receiving Type 11 message with a size of 256B from the FPGA (We are running the DSP in polling mode). We have verified the FPGA can decode Type-11 message from the DSP with its SRIO IP. We are using x4 port configuration and 16-bit Src/Dest Ids. We noticed that for messages coming out the FPGA that the start of the message header is on lane 1 versus the messages coming out the DSP message header starts on lane 0. Could this cause alignment problem with SRIO decoder on the 6678?

  • Hi,

    I have replied the same question on your new thread, could you please close this tread and continue with your new thread for further communication.
    e2e.ti.com/.../1462278

    Thanks,