Hi,
I modified the CSL PCIe example to create a C6678 RC design. It works fine with my FPGA endpoint when the RC was configured in GEN1 mode with 1 lane only. That's the default setting of the reference design. When I changed the RC to work in GEN2 mode with 2 lanes. It didn't work. Linkup failed.
Here is the major change on the code. Modifed the value of PL_LINK_CTRL and PL_GEN2 registers.
pcieRet_e pcieCfgRC(Pcie_Handle handle)
{
.......
.......
/* Setting PL_GEN2 */
memset (&setRegs, 0, sizeof(setRegs));
gen2.numFts = 0xF;
gen2.dirSpd = 1; // 0 -> not to gen2, 1 -> gen2
gen2.lnEn = 2; // 1 -> 1xlane, 2 -> 2xlane
setRegs.gen2 = &gen2;
lnkCtrl.lnkMode = 3;
setRegs.lnkCtrl = &lnkCtrl;
if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
{
System_printf ("SET GEN2 register failed!\n");
return retVal;
}
.....
.....
}
Any idea??? Any working example code for RC+GEN2+2lanes???
Watson