the conflict between EDMA and SRIO in multicore

Jane Mary

Other Parts Discussed in Thread: TMS320C6678

I use multicore to do signal process.Core3 is used to receive data from FPGA using SRIO,the data is stored in DDR3.Core0 uses EDMA to move data from DDR3 to core2 L2.So I have a question:when core3 is storing data in DDR3(writing DDR3),if now core0 want to move the data from DDR3(reading DDR3),does it have confliction because they are using the same bus? And what is the priority between SRIO and DMA? What's more,is there a method if I want to change their priority?

Many thanks!

TMS320C6678
ccs 5.2
pdk_C6678_1_0_0_18

over 9 years ago

0 Ganapathi Dhandapani95 over 9 years ago

TI__Mastermind 28085 points

Hi,

I think the Priority not help for your operation. Both corepac's are not able access the same DDR3 memory at the same time. After the core3 is received data from FPGA via srio and then move the data from DDR3 to core2 L2 memory.

Thanks,

0 Jane Mary over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 170 points

the corepacs do not access the same DDR3 memory.I didn't make it clear.

In my application,the DDR3 is used as ping-pong RAM.For example,core3 is received data from FPGA via srio and store the data begin at 0x82000000.core0 use DMA to move the data from 0x83000000 to core2 L2(0X12800000).So what about this situation?

0 Ganapathi Dhandapani95 over 9 years ago in reply to Jane Mary

TI__Mastermind 28085 points

Hi,

Better to set the high priority to EDMA transfer.

Thanks,

0 Jane Mary over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 170 points

Could I ask why?And how to set the priority?

0 Jane Mary over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 170 points

I am really anxious about how to set the priority.Hope for your answer.Thank you !

0 Ganapathi Dhandapani95 over 9 years ago in reply to Jane Mary

TI__Mastermind 28085 points

Hi,

I am not expert on EDMA, I will check with peripheral expert and get back to you.

You can set the priority of the individual queues through the queue priority register (QUEPRI). Refer the section "EDMA3 Prioritization" in the Keystone EDMA3 Controller User Guide to get the detailed information.

Thanks,

0 Jane Mary over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 170 points

Many thanks!Hope for your reply.

0 Sivaraj Kuppuraj over 9 years ago in reply to Jane Mary

TI__Mastermind 35645 points

Hi,

Thanks for your update.

Basically, the queue priority register (QUEPRI) allows you to program the priority of the individual queues and the priority of the transfer request (TR) associated with the events queued in the queue. For more details, please refer EDMA3 user guide for EDMA prioritization and kindly refer sections 2.14 & 4.2.1.8

http://www.ti.com/lit/ug/sprugs5a/sprugs5a.pdf

Thanks & regards,

Sivaraj K

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the conflict between EDMA and SRIO in multicore