SRIO LOCAL_DIS bit and PEREN in PCR register description mismatch

I am unable to get a DirectIO NREAD from an FPGA to work.  Using 1 port in 4x mode, the NWRITES work quite well with no errors based on debugging the FPGA side. So the link is physically running correctly.  NREAD's arrive correctly at the FPGA, it sends the response correctly according to its debugger, but the C6678 always gets a response timeout (condition code 01 in the LSU_stat). 

The GEL script I use to analyze the registers says that LOCAL_DIS ( = 0) is "discarding packets". The csl_srioAux.h file from the PDK 1.1.2.6 does not have a function to read the LOCAL_DIS bit or to read or write the RESTORE bit, suggesting that maybe this is typically not used or necessary? 

Where should I look to figure out why response packets don't make it?

Thanks in advance.

Mike

I've tried setting the RESTORE bit when I initialize the SRIO but that did not change anything. In fact it seemed to cause errors.
I still can't get a handle on why the NREAD times out when the NWRITES work just fine.  Again, talking to an FPGA in 1 port mode 4x wide.  There is
only 1 core using the SRIO, so I only check the LSU full bit.  After sending the request, I poll on the completion code to tell when it is finished.  It always
comes back as timeout and the memory is not changed.

Here is the code:

      fpgaCmdData[0] = 0xa0a0a0a0;
      fpgaCmdData[1] = 0x05050505;

                        /* Make sure there is space in the Shadow registers to write*/
      while(CSL_SRIO_IsLSUFull(hSrio, LSU1) != 0);

                                       /* This reads REG6 to get the LTID and LCB   */
      CSL_SRIO_GetLSUContextTransaction(hSrio, LSU1, &tcontext, &txnid);

      lsuXfr.rapidIOMSB    = 0;                 // MSW of the destination address. None
      lsuXfr.doorbellValid = 0;                 // no doorbell
      lsuXfr.intrRequest   = 0;                 // No interrupts
      lsuXfr.supInt        = 0;                 // suppress good interrupt = 0 (don't care about interrupts)
      lsuXfr.xambs         = 0;                 // xambs = 0
      lsuXfr.priority      = 0;                 // priority = 0
      lsuXfr.outPortID     = 0;                 // outport id = 0
      lsuXfr.idSize        = 0;                 // id size = 1 for 16bit device IDs
      lsuXfr.srcIDMap      = 1;                 // src id map = 1, using RIO_DEVICEID_REG1
     lsuXfr.dstID         = fpga_Id_8bit;      // destid = 0x0A
      lsuXfr.hopCount      = 0;                 // hop count = 0,
      lsuXfr.doorbellInfo  = 0;                 // doorbell = 0
      lsuXfr.ttype   = 0x4;            // ttype,   NREAD
      lsuXfr.ftype   = 0x2;            // ftype,   NREAD

      lsuXfr.rapidIOLSB    = 0x02000050;                 // LSB of the destination address.
      lsuXfr.dspAddress    = (uint32_t)&fpgaCmdData;  // dsp address is the source for the data write
      lsuXfr.bytecount     = 8;                       // number of bytes to send; always 2 words

      CSL_SRIO_SetLSUTransfer(hSrio, LSU1, &lsuXfr);             //Busy bit is now 0

      do
      {
         CSL_SRIO_GetLSUCompletionCode(hSrio, LSU1, txnid, &completion_code, &context_bit);
      }while (tcontext != context_bit);

Thanks for any help, I'm running out of ideas.

Mike

Not sure about the formatting on the previous post, looks kind of bad, let me try again.

I've tried setting the RESTORE bit when I initialize the SRIO but that did not change anything. In fact it seemed to cause errors.

I still can't get a handle on why the NREAD times out when the NWRITES work just fine. Again, talking to an FPGA in 1 port mode 4x wide. There is only 1 core using the SRIO, so I only check the LSU full bit. After sending the request, I poll on the completion code to tell when it is finished. It always comes back as timeout and the memory is not changed.

Here is the code:

      fpgaCmdData[0] = 0xa0a0a0a0;
      fpgaCmdData[1] = 0x05050505;

                        /* Make sure there is space in the Shadow registers to write*/
      while(CSL_SRIO_IsLSUFull(hSrio, LSU1) != 0);

                                       /* This reads REG6 to get the LTID and LCB   */
      CSL_SRIO_GetLSUContextTransaction(hSrio, LSU1, &tcontext, &txnid);

      lsuXfr.rapidIOMSB    = 0;                 // MSW of the destination address. None
      lsuXfr.doorbellValid = 0;                 // no doorbell
      lsuXfr.intrRequest   = 0;                 // No interrupts
      lsuXfr.supInt        = 0;                 // suppress good interrupt = 0 (don't care about interrupts)
      lsuXfr.xambs         = 0;                 // xambs = 0
      lsuXfr.priority      = 0;                 // priority = 0
      lsuXfr.outPortID     = 0;                 // outport id = 0
      lsuXfr.idSize        = 0;                 // id size = 1 for 16bit device IDs
      lsuXfr.srcIDMap      = 1;                 // src id map = 1, using RIO_DEVICEID_REG1
      lsuXfr.dstID         = fpga_Id_8bit;      // destid = 0x0A
      lsuXfr.hopCount      = 0;                 // hop count = 0,
      lsuXfr.doorbellInfo  = 0;                 // doorbell = 0
      lsuXfr.ttype   = 0x4;            // ttype,   NREAD
      lsuXfr.ftype   = 0x2;            // ftype,   NREAD

      lsuXfr.rapidIOLSB    = 0x02000050;                 // LSB of the destination address.
      lsuXfr.dspAddress    = (uint32_t)&fpgaCmdData;  // dsp address is the source for the data write
      lsuXfr.bytecount     = 8;                       // number of bytes to send; always 2 words

      CSL_SRIO_SetLSUTransfer(hSrio, LSU1, &lsuXfr);             //Busy bit is now 0

      do
      {
         CSL_SRIO_GetLSUCompletionCode(hSrio, LSU1, txnid, &completion_code, &context_bit);
      }while (tcontext != context_bit);

Thanks   Mike

Hi,

Please increase the timeout delay(maximum timeout) and try to test the NREAD operation. 

Have you referred the below thread for Nread transaction timeout?
e2e.ti.com/.../927353

Thanks,

I have looked at that thread. I don't get any hardware errors that I can tell, the link status registers are very clean, no errors at all, I'm not using doorbell, and the ERR_DET bits only indicate a response timeout, no other error shows up in it or any of the other error registers. And the NWRITE works fine. I'm really puzzled where to look.

Please increase the timeout delay(maximum timeout) and try to test the NREAD operation.

This is the current setting, I believe they are at the maximum.

C66xx_0: GEL Output:  ********************************** Port Link Time-Out Control CSR (SP_LT_CTL) ******************************************************

C66xx_0: GEL Output:  TVAL ---> 4.992899 to 6.657199 sec (srio_ip_clk - 312.5 MHz)

C66xx_0: GEL Output:  ********************************** Port Response Time-Out Control CSR (SP_RT_CTL) ******************************************************

C66xx_0: GEL Output:  TIMEOUT_VALUE[31:8] ---> 0x00FFFFFF => 503316450.0 ns

Mike

Have you received the actual data for the NREAD operation?

Try to implement the doorbell interrupt on your setup or disable Packet Response Time-out error enable bit field ERR_EN register.

Ok, so the problem was in the FPGA after all.  The "SRIO core" of the Xilinx fpga was passing the read request to the "application" level which supplied the correct information to the core, but the core never actually sent the data back to the dsp. Something about needing some wait states inserted.  Thank you for the help and suggestions.  I did learn a lot.

Mike

Glad to hear. Thanks for your update.

Hi Michael,

I have some trouble with data transfer between DSP and Xilinx FPGA. After sent read request from DSP to FPGA, I don't get data back.

Did you edit SRIO IP core from Xilinx?

With regards,

Vladimir

Vladimir,

I was not the one working with the Xilinx, that was a colleague that was working on the project with me.  Sorry I don't know the details.

Mike

Hi Michael,

It is very a pity, but thank you for the answer.

With regards,
Vladimir