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I2C EEPROM BOOTING AND IBL DOUBTS

NITHIN BOJJA
Intellectual 505 points

Hi,

   I have  few doubts regarding I2C EEPROM booting and IBL

1. In I2C EEPROM booting readme.txt, it is given that writing .dat/.bin at 0x51,  but I am able to boot keeping switch settings as

                                       4     3   2   1

                        SW-3     1     0   1   1

                         SW-4     0     0   0   0

                        SW-5     0     0   0   0

                        SW-6     0     0   0   0

But SW-5[4] has to be 1 to boot from 0x51. How it is booting from 0x51 when I kept SW-5[4] (GPIO 11) as 0.

2. Can I2C EEPROM can be booted from 0x50?

3. Can I2C EEPROM can be booted from 0x51?

4. Can IBL be loaded in 0x50?

5. I am working on 6678 EVM Rev 3.0 and silicon  rev 2.0. I created dat file for led.out using SPI NOR BOOTING steps and change the switch settings, I was able to see the led blinking. But when I load the multicore image processing demo(default) .bin file through the same procedure and  change the switch settings, I am unable to see the result. But when I booted the image through SPI NOR OVER I2C EEPROM using IBL, I am able to see the result.  If DDR3 initializations are there in the code, is IBL  must (SPI NOR OVER I2C EEPROM)?. How I can boot the same image without using IBL, directly from SPI NOR?.

  • 0
    TI__Mastermind 28085 points
    Hi,

    RBL code not initialize the PLL register properly, so force the DSP to I2C boot mode to initialize the PLL register(workaround implemented in IBL code) and the IBL will boot the DSP as per the boot mode switch setting. IBL required for the following boot modes NOR, NAND, TFTP, Ethernet, SRIO and PCIe. For more information refer keystone boot loader user guide.

    If you want to boot from I2C means you can choose I2C POST boot. IBL is not required for the I2C boot mode. Your EVM switch settings also show I2C POST boot mode. Refer \ti\mcsdk_2_01_02_06\tools\post\docs\README.txt document for flash the binary to EEPROM 0x50.

    MCSDK POST example is a test program that can be programmed to I2C EEPROM and boot directly from I2C bus address 0x50 after POR. It performs board specific tests, such as external memory test, NAND/NOR/EEPROM read test, LED test, etc.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    TI__Mastermind 28085 points
    Refer MCSDK user guide, it should be help you for understanding the IBL.
    processors.wiki.ti.com/.../BIOS_MCSDK_2.0_User_Guide

    For DSP boot mode switch selection refer TMDXEVM6678L EVM Hardware Setup guide
    processors.wiki.ti.com/.../TMDXEVM6678L_EVM_Hardware_Setup

    Refer program_evm_userguide document for all DSP boot modes.
    MCSDK Path: "\ti\mcsdk_2_01_02_06\tools\program_evm\program_evm_userguide.pdf

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 505 points

    Thank you for the reply ganapathy,

    Can you please help me to understand/answer about 4th and 5th  points in my posting.

    Regards

    Nithin

  • 0 in reply to NITHIN BOJJA
    TI__Mastermind 28085 points

    I am not sure the RBL use the specific I2C slave address 0x51 for force IBL boot. If RBL not specified the I2C slave address means you can use any one EEPROM for IBL programming.

    Boot ROM(RBL) code not properly done the PLL initialization sequence on PG 1.0 revision the issue is fixed on PG 2.0 revision chips. Refer "Advisory 8 Multiple PLLs May Not Lock After Power-on Reset Issue" on C6678 Silicon Errata document(SPRZ334G). The workaround should be added before the main PLL initialization sequence inside the application code.

    Thanks,