C6657 DDR3 Autolevelling issue

Hi,
I am using custom board.

Thanks,
Ram.

Hi Raj,

i saw one of the thread and i corrected DQS Timing like this .But still i have the problem.//Correct DQS-DQ timing offset DDR3_CONFIG_REG_1 = 0x01000000;


i am using DDR3 MT41K1G4 – 128 Meg x 4 x 8 banks. i am giving my code what i am using for DDR3 intialization.i am having an input clock of 312.5MHz for DDR3.so the DDR3 clock i am using is 312.5 MHz(PLLD3,PLLM1) and also 625MHz(PLLD7,PLLM1) . in both cases the DDR3 is unstable some times.
Please help me to find why my DDR3 is unstable in some cases.

CSL_BootCfgUnlockKicker();

//platform_delaycycles(50000);
uSleeptime = 50000 ;
while (uSleeptime--) {
asm(" NOP");
}

/**************** 3.3 Leveling Register Configuration ********************/
CSL_BootCfgGetDDRConfig(0, &ddr3config);
ddr3config &= ~(0x007FE000); // clear ctrl_slave_ratio field
CSL_BootCfgSetDDRConfig(0, ddr3config);

CSL_BootCfgGetDDRConfig(0, &ddr3config);
ddr3config |= 0x00200000; // set ctrl_slave_ratio to 0x100
CSL_BootCfgSetDDRConfig(0, ddr3config);

CSL_BootCfgGetDDRConfig(12, &ddr3config);
ddr3config |= 0x08000000; // Set invert_clkout = 1
CSL_BootCfgSetDDRConfig(12, ddr3config);

CSL_BootCfgGetDDRConfig(0, &ddr3config);
ddr3config |= 0xF; // set dll_lock_diff to 15
CSL_BootCfgSetDDRConfig(0, ddr3config);

CSL_BootCfgGetDDRConfig(23, &ddr3config);
ddr3config |= 0x00000200; // See section 4.2.1, set for partial automatic levelling
CSL_BootCfgSetDDRConfig(23, ddr3config);

/**************** 3.3 Partial Automatic Leveling ********************/
//Correct DQS-DQ timing offset
ddr3config = 0x01000000; CSL_BootCfgSetDDRConfig(1, ddr3config);

ddr3config = 0x00; CSL_BootCfgSetDDRConfig(2, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(3, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(4, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(5, ddr3config);
ddr3config = 0x00000033; CSL_BootCfgSetDDRConfig(6, ddr3config);
ddr3config = 0x0000003A; CSL_BootCfgSetDDRConfig(7, ddr3config);
ddr3config = 0x0000002C; CSL_BootCfgSetDDRConfig(8, ddr3config);
ddr3config = 0x0000002C; CSL_BootCfgSetDDRConfig(9, ddr3config);
ddr3config = 0x0000001C; CSL_BootCfgSetDDRConfig(10, ddr3config);

ddr3config = 0x00; CSL_BootCfgSetDDRConfig(14, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(15, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(16, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(17, ddr3config);
ddr3config = 0x000000B7; CSL_BootCfgSetDDRConfig(18, ddr3config);
ddr3config = 0x000000B1; CSL_BootCfgSetDDRConfig(19, ddr3config);
ddr3config = 0x000000A4; CSL_BootCfgSetDDRConfig(20, ddr3config);
ddr3config = 0x000000A4; CSL_BootCfgSetDDRConfig(21, ddr3config);
ddr3config = 0x00000098; CSL_BootCfgSetDDRConfig(22, ddr3config);

/*Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 */
CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
ddrPhyCtrl &= ~(0x00008000);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
ddrPhyCtrl |= (0x00008000);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
ddrPhyCtrl &= ~(0x00008000);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

/***************** 3.4 Basic Controller and DRAM configuration ************/

/* enable configuration */
/* hEmif->SDRAM_REF_CTRL = 0x00006180; */
CSL_EMIF4F_EnableInitRefresh();
CSL_EMIF4F_SetRefreshRate(0x515C);

/* enable configuration */
/* hEmif->SDRAM_REF_CTRL = 0x00006180; */
CSL_EMIF4F_EnableInitRefresh();
CSL_EMIF4F_SetRefreshRate(0x515C);

sdram_tim1.t_wtr = 4;
sdram_tim1.t_rrd = 1;
sdram_tim1.t_rc = 0x20;
sdram_tim1.t_ras = 0x17;
sdram_tim1.t_wr = 0x09;
sdram_tim1.t_rcd = 0x09;
sdram_tim1.t_rp = 0x09;
CSL_EMIF4F_SetTiming1Config(&sdram_tim1);

/* hEmif->SDRAM_TIM_2 = 0x40877FEC; */
sdram_tim2.t_cke = 3;
sdram_tim2.t_rtp = 4;
sdram_tim2.t_xsrd = 0x1FF;
sdram_tim2.t_xsnr = 0x071;
sdram_tim2.t_xp = 3;
sdram_tim2.t_odt = 0;
CSL_EMIF4F_SetTiming2Config (&sdram_tim2);

/* hEmif->SDRAM_TIM_3 = 0x55BF87FF; */
sdram_tim3.t_rasMax = 0xF;
sdram_tim3.t_rfc = 0x06A;
sdram_tim3.t_tdqsckmax = 0;
sdram_tim3.zq_zqcs = 0x3F;
sdram_tim3.t_ckesr = 4;
sdram_tim3.t_csta = 0x5;
sdram_tim3.t_pdll_ul = 0x5;
CSL_EMIF4F_SetTiming3Config (&sdram_tim3);

/* hEmif->DDR_PHY_CTRL_1 = 0x0010010F; */
ddrPHYReadLatency = 0x0F;
ddrPhyCtrl = (0x0010010F);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

/* hEmif->ZQ_CONFIG = 0x70074C1F; */
zqcfg.zqRefInterval = 0x4C1F;
zqcfg.zqZQCLMult = 3;
zqcfg.zqZQCLInterval = 1;
zqcfg.zqSFEXITEn = 1;
zqcfg.zqDualCSEn = 1;
zqcfg.zqCS0En = 1;
zqcfg.zqCS1En = 0;
CSL_EMIF4F_SetOutputImpedanceConfig(&zqcfg);

/* hEmif->PWR_MGMT_CTRL = 0x0; */
pwrmgmtcfg.csTime = 0;
pwrmgmtcfg.srTime = 0;
pwrmgmtcfg.lpMode = 0;
pwrmgmtcfg.dpdEnable = 0;
pwrmgmtcfg.pdTime = 0;
CSL_EMIF4F_SetPowerMgmtConfig (&pwrmgmtcfg);

/* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 */
/* hEmif->SDRAM_CONFIG = 0x63077AB3; */
CSL_EMIF4F_GetSDRAMConfig (&sdramcfg);
sdramcfg.pageSize = 2;
sdramcfg.eBank = 0;
sdramcfg.iBank = 3;
sdramcfg.rowSize = 5;
sdramcfg.CASLatency = 14;
sdramcfg.narrowMode = 1;
sdramcfg.CASWriteLat = 3;
sdramcfg.SDRAMDrive = 1;
sdramcfg.disableDLL = 0;
sdramcfg.dynODT = 2;
sdramcfg.ddrDDQS = 0;
sdramcfg.ddrTerm = 2;
sdramcfg.iBankPos = 0;
sdramcfg.type = 3;
CSL_EMIF4F_SetSDRAMConfig (&sdramcfg);

uSleeptime = 8440336;
while (uSleeptime--) {
asm(" NOP");
}

Thanks,
Ram.

Hi Ram,

The DDRPLL settings you've provided are not valid. You stated that you were using a 312.5MHz input clock and setting (PLLD3,PLLM1) or (PLLD7,PLLM1). These settings would give you a 78.125 MTS or 39.063 MTS DDR interface. These are not valid speeds for DDR3.
What is your target speed for the interface?
Have you populated the REGCALC spreadsheet for your design and modified the GEL?
Have you verified the operation of your interface using the GEL or are you using software?
Can you verify your length matching for all the DDR3 signals?

Regards,
Bill

Hi,

(1)if i have Reference CLK freq 312.5 MHz and DDR3 CLK expected is 666.5 MHz. what are PLLM and PLLD factors?
(2)if i have Reference CLK freq 312.5 MHz and DDR3 CLK expected is 312.5 MHz. what are PLLM and PLLD factors?

Thanks,
Ram.

Hi Bill,

Sorry, I mistakenly entered the PLL values. please see the values i am using .
with reference clock of 312.5MHz, the DDR3 clock i am using is 312.5 MHz(PLLD1,PLLM3) and also 625MHz(PLLD1,PLLM7)

(1)if i have Reference CLK freq 312.5 MHz and DDR3 CLK expected is 625 MHz. what are PLLM and PLLD factors?
(2)if i have Reference CLK freq 312.5 MHz and DDR3 CLK expected is 312.5 MHz. what are PLLM and PLLD factors?
(3)if i have Reference CLK freq 312.5 MHz and DDR3 CLK expected is 666.5 MHz. what are PLLM and PLLD factors?

Thanks,
Ram.

Hi Ram,

The DDR clock values that you are requesting are still a little confusing. DDR3 memories come in speed grades. The C6657 supports three of the specified speed grades which are 800MT/s, 1066.66MT/s and 1333.333MT/s. These three use a DDR clock frequency of 400MHz, 533.333MHz and 666.666MHz respectively. The 312.5MHz is an odd frequency for the DDR reference clock input and it will not generate these clocks exactly so you want to program your PLL to get as close to the ideal DDR clock frequency without going over that frequency.

You haven't given me the speed grade of the memories that you are using but I will assume you have 1333MT/s memory devices and need a clock frequency as close to 666.666MHz as possible. Ideally, you want to keep the multiplier as small as possible. A larger multiplier will increase the lock time for the PLL.

For a shorter lock time use the following

PLLD=3, PLLM=16 -> DDR clock= 664.063MHz. 

If you can tolerate a longer lock time use the following

PLLD=14, PLLM=63 -> DDR clock = 666.666MHz

The equation for the PLL output can be found in the KeyStone Architecture PLL User's Guide. You can use those equations to calculate the multiplier and divider for the lower memory speed grades if necessary. 

Regards,

Bill

Hi,
As you assumed is right, we are using 1333.333MT/s and expecting 666.666MHz DDR3 Clock. i saw the formulas what i am doing is right.
firstly i used before PLLD=3, PLLM=16 to get values 664.0625MHz ,but my DDR3 Memory test fails every time. so i try to reduce the clock frequency (which is ok for us). so i am using PLLD1,PLLM7 which gives 625MHz with the same formulas. But i think we are deviating from the question i asked at the beginning.
has anyone done the work around for Autolevelling?please help me in this case.

Thanks,
Ram.