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Keystone II DDR3Register Calc spreadsheet usage

Hi,


I need to modify U-BOOT DDR3 functionality for our custom board.

In the excel spreadsheet (http://www.ti.com/lit/zip/sprabx7), sheet "PHY Registers", there are few "read-modify-write mask 0xXXXX_XXXX" comments.

E.g. DDR3_DCR register value for me is 0x0000_040B, and it indicates mask of 0x2800_0000 (UDIMM & NOSRA bits are set). For me it looks like the only option is that UDIMM & NOSRA bits on the register should be preserved, and all other bits set/cleared by the value.

But then on DDR3_DX2GCR, the value is 0x7C00_0E81 and the mask is 0x0000_0001 (DXEN bit is set). And in this case the DXEN is most interesting bit to set/clear => my interpretation is that mask bits should be set by the value, and all others preserved. But the value has lots of other bits than DXEN, which would be discarded if masked out.

Questions being:

1. What is the proper interpretation of "read-modify-write mask" ?

2. Are the indicated mask values really correct ?

3. Do the register values (with indicated mask) have bits set outside of mask bits (effectively being ignored during rd-mod-wr) ?


  BR, -Topi

  • Hi Topi,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    We will get back to you on the above query shortly. Thank you for your patience.

  • Hi Topi,
    I recommend you to update the gel file for DDR init and test, then you can update the same init values on u-boot loader source.
    Thank you.
  • Topi,

    You misunderstand the intent of the read-modify-write mask.  It is a negative-logic mask.  For instance the PGCR1 mask is 0x0180_0184.  It would be used to CLEAR all of the bits set.  Therefore, during the init sequence, you would invert it (ones complement) and then AND it with the value read from the register.  Then once the bits of interest are cleared, you want to OR the desired values into these bits.  Here is an example that explicitly masks each field:

    DDR3A_PGCR1 &= ~( 0x01800184);
    DDR3A_PGCR1 |= ((1 << 2) & 0x00000004); //WLSTEP = [1]
    DDR3A_PGCR1 |= ((1 << 7) & 0x00000180);  //IODDRM = [01]
    DDR3A_PGCR1 |= ((1 << 23) & 0x01800000);  //ZCKSEL= [01]

    The Init App Note breaks this into pieces and simplifies but does the same thing:

    // Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1
    // (address offset 0x00C). All other fields must be left at their default values by using a
    // read-modify-write sequence to preserve the other bits. ZCKSEL is chosen from the register
    // calculation spreadsheet based on the main PLL rate.
    DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
    DDR3A_PGCR1 &= ~( 0x00000180);
    DDR3A_PGCR1 |= (( 1 << 7) & 0x00000180);
    DDR3A_PGCR1 &= ~( 0x01800000);
    DDR3A_PGCR1 |= (( 1 << 23) & 0x01800000);

    Tom

     

  • All bits outside the read-modify-write mask must be left unchanged.