Hi,
I need to modify U-BOOT DDR3 functionality for our custom board.
In the excel spreadsheet (http://www.ti.com/lit/zip/sprabx7), sheet "PHY Registers", there are few "read-modify-write mask 0xXXXX_XXXX" comments.
E.g. DDR3_DCR register value for me is 0x0000_040B, and it indicates mask of 0x2800_0000 (UDIMM & NOSRA bits are set). For me it looks like the only option is that UDIMM & NOSRA bits on the register should be preserved, and all other bits set/cleared by the value.
But then on DDR3_DX2GCR, the value is 0x7C00_0E81 and the mask is 0x0000_0001 (DXEN bit is set). And in this case the DXEN is most interesting bit to set/clear => my interpretation is that mask bits should be set by the value, and all others preserved. But the value has lots of other bits than DXEN, which would be discarded if masked out.
Questions being:
1. What is the proper interpretation of "read-modify-write mask" ?
2. Are the indicated mask values really correct ?
3. Do the register values (with indicated mask) have bits set outside of mask bits (effectively being ignored during rd-mod-wr) ?
BR, -Topi