Hi,
I'm trying to implement DDR3 initialization as per SPRABX7 ("Keystone II DDR3 Initialization").
On "Example 4. DDR PHY Initialization"
//Assert DDR PHY reset after PLL enabled DDR3APLLCTL1 = DDR3APLLCTL1 | 0x80000000; for(i=0;i<delay;i++); DDR3APLLCTL1 = DDR3APLLCTL1 & 0x7FFFFFFF; //Release DDR PHY reset
SPRS866E states (page 307) that DDR3APLLCTL1 bit 31 is reserved, not phy reset as the code snippet suggests.
On DDR3 manual (SPRUHN7C) I can find two different PHY reset bits:
PIR bit 6 (PHYRST); and
PGCR1 bit 25 (PHYHRST).
1. What is the proper PHY reset sequence needed before polling IDONE?
BR, -Topi
