DDR3 Initialization6678

Hi Nithin,

There is an example of multi stage boot in the MCSDK 2.x if you are using IBL like on the EVM. You can find the example under mcsdk_2_01_02_06\tools\boot_loader\examples\srio\srioboot_ddrinit.that example shows two stage booting on the EVM using IBL functionality.

In case you don`t have an IBL and are directly booting from SPI, you can do the following.

Step1 : Add _romtBootReentry_addr=0x20b00008; at the top of your .cmd file. this is the memory location in the L2ROM to re-enter bootROM.

Step 2: In your source file, you will need to replace the boot parameter table to let the boot ROM know where your second stage boot table is located. Boot parameter table is located at 0x00873680 (Refer 2.4 in Data Manual). Description of the boot parameter table structure is given in section 2.5.3 of the data manual. You can keep most of the field of the parameter the same but replace the Read Addr MSW and Read Addr LSW to point to second stage. and then add the following code to your first stagesource when you want to re-enter the bootROM.

main(){

void (*fcn)(void);

--------

/*Replace boot parameter table*/

/*Do DDR initialization*/

----------

/* Re-enter the boot rom without sampling the boot strap pins again to allow the modified boot parameter table to be used for boot */
    fcn = (void (*)(void))&romtBootReentry_addr;
    (*fcn)();

}

For second part of your question. Yes, you might be able to initialize DDR without re-entering bootROM but this requires you to use the DDR configuration table as shown in the example I have attached below:

3808.SPIboot_ddr.zip

The example attached was created for C6657 and not for C6678 so you will need to change the tiboot.h file and replace the DDR configuration(BOOT_EMIF4_TBL_T) to match your platform.Memory map for placing the DDR configuration table is different between the 2 devices so you will have to chnage the location of DDR_CFG to 0x00873500 instead of 0x8ffd20 in the .cmd file. Also look at the way the spiboot.cmd places the DDR configuration table in the correct location before any sections are loaded into DDR. You need to have the same setting in your linker command file. I mean the .emif section must be placed in DDR_CFG space before any code or text section is loaded in DDR.

Also, a note here, the  correct DDR initialization sequence has been modified since the last time the ROM was revised so we have seen that on this platform the device can initialize DDR only at lower speeds.

Regards,

Rahul

Thank You Rahul,

It is working. Thank You very much for your help.

Regards

Nithin

Hi Rahul,

My application is using DDR3 and I placed my application after some offset(sector2) from DDR3 Initialization. As you suggested I used void (*funcptr)( void ) to jump to my application and before that I am Initializing DDR3.

Thank You

Regards

Nithin