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Queries about TI DSP C6674 ethernet and srio accessing by all 4 cores

Hi,


We had a design which is finalized with TI DSP C6674, we have the following queries about multi-core/all cores :

1. can each core have individual ip address

2. can each core send/receive data over ethernet on individual sockets/ports

3. can each core access srio to receive or transmit data

4. can each core run fft algorithm

5. ti supports grey scale transform? if yes can it run on all cores

6. is it possible to reset a dsp by itself with updating any registers

Awaiting for your valuable response.

Thanks

Mani Kumar