C6678 Rev2.0 PCIe BOOT

Hi,

Has PCIe direct boot (without I2C EEPROM) been tested with Rev 2.0 C6678 device?
If yes, we would like to understand as to how it was done? (EVM details and any Hardware or FPGA changes that were made to work in PCIe boot, this is because the FPGA code always forces C6678 to I2C boot mode)

IBL is required for C6678 rev 2.0 chips PCIe boot mode.

After power cycle (OFF and ON) of the C6678 EVM, we observe the DEVSTAT register value is 0x1 or 0x10001 (no boot mode). After pressing FULL_RESET or WARM_RESET button multiple times, the DEVSTAT register value reads 0x80B or 0x1080B (i2c boot mode). We are yet to understand the reason behind this behavior. Please let us know if any of you have observed this and possible reasoning.

I will check with hardware team and get back to you.

When SW9 Pin #1 (signal is PCIESSEN) on C6678 EVM is off (Set to 1), the linux host PC never boots. The host PC boots when the SW9 pin #1 is set to ON (set to 0) and it does not detect the C6678 EVM as PCIe endpoint. Can you please clarify this to us?

Some Host PCs are not properly detect the DSP, please try to test the same on different Host PC. Also refer the PCIe FAQ wiki link
processors.wiki.ti.com/.../PCI_Express_%28PCIe%29_Resource_Wiki_for_Keystone_Devices

Thanks,

Hi Ganapathi,

1. What do you mean by IBL is required? The C6678 Rev 2.0 chip errata says that PLL fix is taken care and no I2C EEPROM is required for PCIe boot. Can you please be more elaborate here?
2. I will await your response on this.
3. I will go through the shared wiki link.

Regards,
Shareef

Yes, the PLL errata is fixed on C6678 rev 2.0 chips, but DSP PCIe clock(FCLK) issue is not fixed on the latest EVM revision. For more information refer section “2.4 Clock Domains” on TMDSEVM6678L EVM Technical Reference Manual. This workaround is enough for PCIe boot, you can implement on your secondary boot loader.

Hi Ganapathi,

Thanks, but I don't see anything wrong with the FCLK of the latest EVM Revision (3.0). Below is the manual link that I referred, even if there is a hardware issue in EVM board how can the IBL running on C6678 fix it?

wfcache.advantech.com/.../TMDSEVM6678L_Technical_Reference_Manual_2V01_0320.pdf

Regards,
Shareef

Please take a look at EVM known issues document on EVM manufacture link.
www2.advantech.com/.../6678le_download3.aspx

EVM FPGA bit file force the DSP to I2C boot mode and then initialize the internal PCIe reference clock to switch the PCIE clock source from the CDCE62005 (set BM_GPIO_10 at “ON” with logic low).

Thanks,

Hi Ganapathi,

Can you please explain in more detail?

Why should the EVM FPGA change the PCIe reference clocks, since the Endpoint can choose to have its own reference clock (CDCE62005) and need not use the PCIE REFCLK provided by the host?

Even if it chooses to use the external PCIE REFCLK, it need not force the C6678 to I2C boot, instead FPGA can change the clock source before bringing C6678 out of reset? 

Am I missing something here?

Regards,

Shareef

Hi,

ROM PG 2.0 with the PLL and PCIE fix, but still have enumeration problems with PC if using RBL, so we have to keep the IBL PCIE workaround.

This is the issue where there are some PCIe ‘fix-up’ values in the IBL that are needed when booting the C6678 EVM in certain PCIe-based computer motherboards. When using RBL PCIe boot, it always fails.

With the default FPGA image on C6678 EVM, it always route the bootmode to use IBL to boot PCIe. If you want to boot DSP RBL PCIe boot, you need to modified the FPGA image and use it.

Thanks,

Hi Ganapathi,

Thanks, here are some more queries and seek your answers for each of them.

1. We need to connect the C6678 EVM to PC and verify the PCIe RBL boot. This is because in the final hardware, there is no I2C EEPROM connected to C6678 and that C6678 is set to RBL PCIe boot. I hope this is possible to boot C6678 from RBL PCIe boot, please confirm.

2. If there are some PCIe 'fix up' values in the IBL for PCIe RBL boot, why was that not present in the C6678 Errata/Advisory?

3. Why is that C6678 PCIe endpoint does not get detected in few PCs?

4. Can the updated FPGA image be shared with us? The FPGA files present in the Advantech website are not complete as there are project and constraints file missing for us to re-build the FPGA. Can you please help us on this?

Regards,

Shareef