Hi,
Currently, we plan to migrate from old TMS320C6414T to Keystone DSP. In current design we use following interface:
HPI: 32bit@25MHz
EMIFA: 32bit@100MHz sync mode
MsBsp: all 3 streams run @100MHz for real time data.
the new device we plan to use is 320C665x(eg 320c6657). Question is:
1, for our EMIFA, 32bit@100MHz synchronous. the EMIF of the 320c6657 cannot support our current system, because of slow performance. So the best interface to communicate with our fpga may be PCIe. Does 320C6657, configued at x2 lane, provide 10Gbps speed?
2, for three MsBSP run @100 MHz for real-time data processing. The new 320C6657 only has 2x MsBSPs. It looks like best way is to use rapidIo to replace the MsBSPs. Our realtime data is 16 bit streams. So if we just transfer the 16 bit data at a time via rapidio, the performance will be lower than current design. If we buffer these data in fpga and transfer at same time, it will introduce latency and lower the core performance. So what is best trade off in this case? Is there any info/doc on performance of payload size vs the data rate? I plan to use 2x port for replacement of the MsBSPs; another 1x port for replacement of HPI interface (downloading code and communicate between dsp and main processor)?
3, new dsp may needs bring OS and drivers for support all feature as well as more buffer for dsp operating. Is there any estimate how much memory normally required to store and run the new dsp os & drivers?
Thanks in advance for your help.
shiquan